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‎llvm/test/Transforms/LoopVectorize/X86/pr39160.ll‎

Lines changed: 66 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,75 +1,71 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
12
; RUN: opt -passes=loop-vectorize -S < %s 2>&1 | FileCheck %s
23

34
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
45
target triple = "x86_64-unknown-linux-gnu"
56

67
; Make sure that we can compile the test without crash.
7-
define void @barney(ptr %dst, i1 %arg) {
8-
9-
; CHECK-LABEL: @barney(
10-
; CHECK: middle.block:
11-
12-
bb:
13-
br label %bb2
14-
15-
bb2: ; preds = %bb2, %bb
16-
%tmp4 = icmp slt i32 poison, 0
17-
br i1 %tmp4, label %bb2, label %bb5
18-
19-
bb5: ; preds = %bb2
20-
br label %bb19
21-
22-
bb18: ; preds = %bb33
23-
ret void
24-
25-
bb19: ; preds = %bb36, %bb5
26-
%tmp21 = phi i64 [ poison, %bb36 ], [ 2, %bb5 ]
27-
%tmp22 = phi i32 [ %tmp65, %bb36 ], [ poison, %bb5 ]
28-
br label %bb50
29-
30-
bb33: ; preds = %bb62
31-
br i1 %arg, label %bb18, label %bb36
32-
33-
bb36: ; preds = %bb33
34-
br label %bb19
35-
36-
bb46: ; preds = %bb50
37-
br i1 %arg, label %bb48, label %bb59
38-
39-
bb48: ; preds = %bb46
40-
%tmp49 = add i32 %tmp52, 14
41-
ret void
42-
43-
bb50: ; preds = %bb50, %bb19
44-
%tmp52 = phi i32 [ %tmp55, %bb50 ], [ %tmp22, %bb19 ]
45-
%tmp53 = phi i64 [ %tmp56, %bb50 ], [ 1, %bb19 ]
46-
%gep = getelementptr inbounds i8, ptr %dst, i64 %tmp53
47-
store i8 1, ptr %gep
48-
%tmp54 = add i32 %tmp52, 12
49-
%tmp55 = add i32 %tmp52, 13
50-
%tmp56 = add nuw nsw i64 %tmp53, 1
51-
%tmp58 = icmp ult i64 %tmp53, poison
52-
br i1 %tmp58, label %bb50, label %bb46
53-
54-
bb59: ; preds = %bb46
55-
br label %bb62
56-
57-
bb62: ; preds = %bb68, %bb59
58-
%tmp63 = phi i32 [ %tmp65, %bb68 ], [ %tmp55, %bb59 ]
59-
%tmp64 = phi i64 [ %tmp66, %bb68 ], [ %tmp56, %bb59 ]
60-
%tmp65 = add i32 %tmp63, 13
61-
%tmp66 = add nuw nsw i64 %tmp64, 1
62-
%tmp67 = icmp ult i64 %tmp66, %tmp21
63-
br i1 %tmp67, label %bb68, label %bb33
64-
65-
bb68: ; preds = %bb62
66-
br label %bb62
67-
}
688

699
define i32 @foo(ptr addrspace(1) %p) {
70-
71-
; CHECK-LABEL: foo
72-
; CHECK: middle.block:
10+
; CHECK-LABEL: define i32 @foo(
11+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) {
12+
; CHECK-NEXT: [[ENTRY:.*]]:
13+
; CHECK-NEXT: br label %[[OUTER:.*]]
14+
; CHECK: [[OUTER]]:
15+
; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
16+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[OUTER_LATCH]] ]
17+
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDVAR]], 1
18+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP0]], 8
19+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
20+
; CHECK: [[VECTOR_PH]]:
21+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP0]], 8
22+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP0]], [[N_MOD_VF]]
23+
; CHECK-NEXT: [[TMP1:%.*]] = add i32 1, [[N_VEC]]
24+
; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[N_VEC]], 2
25+
; CHECK-NEXT: [[TMP3:%.*]] = add i32 6, [[TMP2]]
26+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
27+
; CHECK: [[VECTOR_BODY]]:
28+
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
29+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
30+
; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
31+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 6, i32 8, i32 10, i32 12>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
32+
; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 8)
33+
; CHECK-NEXT: [[TMP4]] = or <4 x i32> [[VEC_PHI]], [[VEC_IND]]
34+
; CHECK-NEXT: [[TMP5]] = or <4 x i32> [[VEC_PHI1]], [[STEP_ADD]]
35+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
36+
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 8)
37+
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
38+
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
39+
; CHECK: [[MIDDLE_BLOCK]]:
40+
; CHECK-NEXT: [[BIN_RDX:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]]
41+
; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[BIN_RDX]])
42+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP0]], [[N_VEC]]
43+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[OUTER_LATCH]], label %[[SCALAR_PH]]
44+
; CHECK: [[SCALAR_PH]]:
45+
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER]] ]
46+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 1, %[[OUTER]] ]
47+
; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ 6, %[[OUTER]] ]
48+
; CHECK-NEXT: br label %[[INNER:.*]]
49+
; CHECK: [[INNER]]:
50+
; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ [[TMP10:%.*]], %[[INNER]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]
51+
; CHECK-NEXT: [[A:%.*]] = phi i32 [ [[TMP11:%.*]], %[[INNER]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
52+
; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[TMP9:%.*]], %[[INNER]] ], [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ]
53+
; CHECK-NEXT: [[TMP9]] = add i32 [[B]], 2
54+
; CHECK-NEXT: [[TMP10]] = or i32 [[TMP8]], [[B]]
55+
; CHECK-NEXT: [[TMP11]] = add nuw nsw i32 [[A]], 1
56+
; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
57+
; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i64 [[IV]], [[TMP12]]
58+
; CHECK-NEXT: br i1 [[TMP13]], label %[[INNER]], label %[[OUTER_LATCH]], !llvm.loop [[LOOP3:![0-9]+]]
59+
; CHECK: [[OUTER_LATCH]]:
60+
; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP10]], %[[INNER]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ]
61+
; CHECK-NEXT: store atomic i32 [[DOTLCSSA]], ptr addrspace(1) [[P]] unordered, align 4
62+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
63+
; CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[IV]], 63
64+
; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
65+
; CHECK-NEXT: br i1 [[TMP14]], label %[[EXIT:.*]], label %[[OUTER]]
66+
; CHECK: [[EXIT]]:
67+
; CHECK-NEXT: ret i32 0
68+
;
7369

7470
entry:
7571
br label %outer
@@ -98,3 +94,9 @@ outer_latch: ; preds = %inner
9894
exit: ; preds = %outer_latch
9995
ret i32 0
10096
}
97+
;.
98+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
99+
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
100+
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
101+
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
102+
;.

‎llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll‎

Lines changed: 34 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
1-
; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -enable-interleaved-mem-accesses=true < %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
2+
; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 \
3+
; RUN: -enable-interleaved-mem-accesses=true < %s | FileCheck %s
24

35
; Make sure the vectorizer can handle this loop: The strided load is only used
46
; by the loop's exit condition, which is not vectorized, and is therefore
@@ -29,10 +31,31 @@
2931
%0 zeroinitializer], align 8
3032

3133
define dso_local void @test_dead_load(i32 %arg) {
32-
; CHECK-LABEL: @test_dead_load(
33-
; CHECK: vector.body:
34-
; CHECK: %wide.vec = load <16 x i32>, ptr %3, align 8
35-
; CHECK: %strided.vec = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
34+
; CHECK-LABEL: define dso_local void @test_dead_load(
35+
; CHECK-SAME: i32 [[ARG:%.*]]) {
36+
; CHECK-NEXT: [[BB1:.*:]]
37+
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
38+
; CHECK: [[VECTOR_PH]]:
39+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
40+
; CHECK: [[VECTOR_BODY]]:
41+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
42+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
43+
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], 52
44+
; CHECK-NEXT: br i1 [[TMP0]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
45+
; CHECK: [[MIDDLE_BLOCK]]:
46+
; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
47+
; CHECK: [[SCALAR_PH]]:
48+
; CHECK-NEXT: br label %[[BB2:.*]]
49+
; CHECK: [[BB2]]:
50+
; CHECK-NEXT: [[TMP:%.*]] = phi ptr [ [[TMP6:%.*]], %[[BB2]] ], [ getelementptr (i8, ptr @[[GLOB0:[0-9]+]], i64 832), %[[SCALAR_PH]] ]
51+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[TMP0]], ptr [[TMP]], i64 0, i32 1
52+
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
53+
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 258
54+
; CHECK-NEXT: [[TMP6]] = getelementptr inbounds [[TMP0]], ptr [[TMP]], i64 1
55+
; CHECK-NEXT: br i1 [[TMP5]], label %[[BB65:.*]], label %[[BB2]], !llvm.loop [[LOOP3:![0-9]+]]
56+
; CHECK: [[BB65]]:
57+
; CHECK-NEXT: unreachable
58+
;
3659
bb1:
3760
br label %bb2
3861

@@ -47,3 +70,9 @@ bb2:
4770
bb65:
4871
unreachable
4972
}
73+
;.
74+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
75+
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
76+
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
77+
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
78+
;.

‎llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll‎

Lines changed: 27 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -3,33 +3,40 @@
33

44
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
55

6-
define void @test() {
6+
define void @test(i32 %tc, ptr %p) {
77
; CHECK-LABEL: @test(
88
; CHECK-NEXT: br label [[FOR_BODY_LR_PH_I_I_I:%.*]]
99
; CHECK: for.body.lr.ph.i.i.i:
10-
; CHECK-NEXT: br i1 poison, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
10+
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TC:%.*]], -1
11+
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
12+
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
13+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
14+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
1115
; CHECK: vector.ph:
16+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4
17+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
1218
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
1319
; CHECK: vector.body:
1420
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
1521
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
16-
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], poison
17-
; CHECK-NEXT: br i1 [[TMP1]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
22+
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
23+
; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
1824
; CHECK: middle.block:
19-
; CHECK-NEXT: br i1 poison, label [[FOR_END_I_I_I:%.*]], label [[SCALAR_PH]]
25+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
26+
; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END_I_I_I:%.*]], label [[SCALAR_PH]]
2027
; CHECK: scalar.ph:
21-
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ poison, [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_LR_PH_I_I_I]] ]
28+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_LR_PH_I_I_I]] ]
2229
; CHECK-NEXT: br label [[FOR_BODY_I_I_I:%.*]]
2330
; CHECK: for.body.i.i.i:
2431
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC_I_I_I:%.*]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
2532
; CHECK-NEXT: br label [[FOR_INC_I_I_I]]
2633
; CHECK: for.inc.i.i.i:
2734
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
2835
; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
29-
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], poison
36+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[TC]]
3037
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY_I_I_I]], label [[FOR_END_I_I_I]], !llvm.loop [[LOOP3:![0-9]+]]
3138
; CHECK: for.end.i.i.i:
32-
; CHECK-NEXT: [[LCSSA:%.*]] = phi ptr [ poison, [[FOR_INC_I_I_I]] ], [ poison, [[MIDDLE_BLOCK]] ]
39+
; CHECK-NEXT: [[LCSSA:%.*]] = phi ptr [ [[P:%.*]], [[FOR_INC_I_I_I]] ], [ [[P]], [[MIDDLE_BLOCK]] ]
3340
; CHECK-NEXT: unreachable
3441
;
3542
br label %for.body.lr.ph.i.i.i
@@ -44,11 +51,11 @@ for.body.i.i.i:
4451
for.inc.i.i.i:
4552
%indvars.iv.next = add i64 %indvars.iv, 1
4653
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
47-
%exitcond = icmp ne i32 %lftr.wideiv, poison
54+
%exitcond = icmp ne i32 %lftr.wideiv, %tc
4855
br i1 %exitcond, label %for.body.i.i.i, label %for.end.i.i.i
4956

5057
for.end.i.i.i:
51-
%lcssa = phi ptr [ poison, %for.inc.i.i.i ]
58+
%lcssa = phi ptr [ %p, %for.inc.i.i.i ]
5259
unreachable
5360
}
5461

@@ -73,37 +80,37 @@ L1:
7380
}
7481

7582
; This loop has different uniform instructions before and after LCSSA.
76-
define void @test3() {
83+
define void @test3(ptr %p) {
7784
; CHECK-LABEL: @test3(
7885
; CHECK-NEXT: entry:
79-
; CHECK-NEXT: [[ADD41:%.*]] = add i32 poison, poison
86+
; CHECK-NEXT: [[ADD41:%.*]] = add i32 3, 3
8087
; CHECK-NEXT: [[IDXPROM4736:%.*]] = zext i32 [[ADD41]] to i64
81-
; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
88+
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
8289
; CHECK: while.body:
83-
; CHECK-NEXT: [[IDXPROM4738:%.*]] = phi i64 [ [[IDXPROM47:%.*]], [[WHILE_BODY]] ], [ [[IDXPROM4736]], [[ENTRY:%.*]] ]
84-
; CHECK-NEXT: [[POS_337:%.*]] = phi i32 [ [[INC46:%.*]], [[WHILE_BODY]] ], [ [[ADD41]], [[ENTRY]] ]
90+
; CHECK-NEXT: [[IDXPROM4738:%.*]] = phi i64 [ [[IDXPROM47:%.*]], [[VECTOR_BODY]] ], [ [[IDXPROM4736]], [[ENTRY:%.*]] ]
91+
; CHECK-NEXT: [[POS_337:%.*]] = phi i32 [ [[INC46:%.*]], [[VECTOR_BODY]] ], [ [[ADD41]], [[ENTRY]] ]
8592
; CHECK-NEXT: [[INC46]] = add i32 [[POS_337]], 1
86-
; CHECK-NEXT: [[ARRAYIDX48:%.*]] = getelementptr inbounds [1024 x i8], ptr poison, i64 0, i64 [[IDXPROM4738]]
93+
; CHECK-NEXT: [[ARRAYIDX48:%.*]] = getelementptr inbounds [1024 x i8], ptr [[P:%.*]], i64 0, i64 [[IDXPROM4738]]
8794
; CHECK-NEXT: store i8 0, ptr [[ARRAYIDX48]], align 1
8895
; CHECK-NEXT: [[AND43:%.*]] = and i32 [[INC46]], 3
8996
; CHECK-NEXT: [[CMP44:%.*]] = icmp eq i32 [[AND43]], 0
9097
; CHECK-NEXT: [[IDXPROM47]] = zext i32 [[INC46]] to i64
91-
; CHECK-NEXT: br i1 [[CMP44]], label [[WHILE_END:%.*]], label [[WHILE_BODY]]
98+
; CHECK-NEXT: br i1 [[CMP44]], label [[WHILE_END:%.*]], label [[VECTOR_BODY]]
9299
; CHECK: while.end:
93-
; CHECK-NEXT: [[INC46_LCSSA:%.*]] = phi i32 [ [[INC46]], [[WHILE_BODY]] ]
100+
; CHECK-NEXT: [[INC46_LCSSA:%.*]] = phi i32 [ [[INC46]], [[VECTOR_BODY]] ]
94101
; CHECK-NEXT: [[ADD58:%.*]] = add i32 [[INC46_LCSSA]], 4
95102
; CHECK-NEXT: ret void
96103
;
97104
entry:
98-
%add41 = add i32 poison, poison
105+
%add41 = add i32 3, 3
99106
%idxprom4736 = zext i32 %add41 to i64
100107
br label %while.body
101108

102109
while.body:
103110
%idxprom4738 = phi i64 [ %idxprom47, %while.body ], [ %idxprom4736, %entry ]
104111
%pos.337 = phi i32 [ %inc46, %while.body ], [ %add41, %entry ]
105112
%inc46 = add i32 %pos.337, 1
106-
%arrayidx48 = getelementptr inbounds [1024 x i8], ptr poison, i64 0, i64 %idxprom4738
113+
%arrayidx48 = getelementptr inbounds [1024 x i8], ptr %p, i64 0, i64 %idxprom4738
107114
store i8 0, ptr %arrayidx48, align 1
108115
%and43 = and i32 %inc46, 3
109116
%cmp44 = icmp eq i32 %and43, 0

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