[AMDGPU] revert xor.ll si-annotate-cf.ll changes

Author: justinfargnoli

llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll

@@ -7,17 +7,15 @@ define amdgpu_kernel void @break_inserted_outside_of_loop(ptr addrspace(1) %out,
 ; SI:       ; %bb.0: ; %main_body
 ; SI-NEXT:    s_load_dword s0, s[2:3], 0xb
 ; SI-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, -1, 0
+; SI-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-NEXT:    v_and_b32_e32 v0, s0, v0
 ; SI-NEXT:    v_and_b32_e32 v0, 1, v0
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
-; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_bitcmp1_b32 s0, 0
-; SI-NEXT:    s_cselect_b64 s[0:1], -1, 0
-; SI-NEXT:    s_and_b64 s[4:5], s[0:1], vcc
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:  .LBB0_1: ; %ENDIF
 ; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
-; SI-NEXT:    s_and_b64 s[6:7], exec, s[4:5]
-; SI-NEXT:    s_or_b64 s[0:1], s[6:7], s[0:1]
+; SI-NEXT:    s_and_b64 s[4:5], exec, vcc
+; SI-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]
 ; SI-NEXT:    s_andn2_b64 exec, exec, s[0:1]
 ; SI-NEXT:    s_cbranch_execnz .LBB0_1
 ; SI-NEXT:  ; %bb.2: ; %ENDLOOP
@@ -34,17 +32,15 @@ define amdgpu_kernel void @break_inserted_outside_of_loop(ptr addrspace(1) %out,
 ; FLAT:       ; %bb.0: ; %main_body
 ; FLAT-NEXT:    s_load_dword s0, s[2:3], 0x2c
 ; FLAT-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
+; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
+; FLAT-NEXT:    v_and_b32_e32 v0, s0, v0
 ; FLAT-NEXT:    v_and_b32_e32 v0, 1, v0
 ; FLAT-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
-; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
-; FLAT-NEXT:    s_bitcmp1_b32 s0, 0
-; FLAT-NEXT:    s_cselect_b64 s[0:1], -1, 0
-; FLAT-NEXT:    s_and_b64 s[4:5], s[0:1], vcc
 ; FLAT-NEXT:    s_mov_b64 s[0:1], 0
 ; FLAT-NEXT:  .LBB0_1: ; %ENDIF
 ; FLAT-NEXT:    ; =>This Inner Loop Header: Depth=1
-; FLAT-NEXT:    s_and_b64 s[6:7], exec, s[4:5]
-; FLAT-NEXT:    s_or_b64 s[0:1], s[6:7], s[0:1]
+; FLAT-NEXT:    s_and_b64 s[4:5], exec, vcc
+; FLAT-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]
 ; FLAT-NEXT:    s_andn2_b64 exec, exec, s[0:1]
 ; FLAT-NEXT:    s_cbranch_execnz .LBB0_1
 ; FLAT-NEXT:  ; %bb.2: ; %ENDLOOP

llvm/test/CodeGen/AMDGPU/xor.ll

@@ -182,12 +182,8 @@ define amdgpu_kernel void @v_xor_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
 ; SI-NEXT:    s_mov_b32 s8, s4
 ; SI-NEXT:    s_mov_b32 s9, s5
+; SI-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; SI-NEXT:    v_and_b32_e32 v0, 1, v0
-; SI-NEXT:    v_and_b32_e32 v1, 1, v1
-; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
-; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], 1, v1
-; SI-NEXT:    s_xor_b64 s[0:1], vcc, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
 ; SI-NEXT:    buffer_store_byte v0, off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
@@ -206,12 +202,8 @@ define amdgpu_kernel void @v_xor_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
-; VI-NEXT:    v_and_b32_e32 v3, 1, v4
+; VI-NEXT:    v_xor_b32_e32 v2, v4, v2
 ; VI-NEXT:    v_and_b32_e32 v2, 1, v2
-; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v3
-; VI-NEXT:    v_cmp_eq_u32_e64 s[0:1], 1, v2
-; VI-NEXT:    s_xor_b64 s[0:1], vcc, s[0:1]
-; VI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]
 ; VI-NEXT:    flat_store_byte v[0:1], v2
 ; VI-NEXT:    s_endpgm
   %a = load volatile i1, ptr addrspace(1) %in0
@@ -820,4 +812,4 @@ define amdgpu_kernel void @vector_xor_literal_i64(ptr addrspace(1) %out, ptr add
   %or = xor i64 %loada, 22470723082367
   store i64 %or, ptr addrspace(1) %out
   ret void
-}
+}