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[Xtensa] Fix address operands.
1 parent 06b3708 commit 2ed0a8a

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6 files changed

+84
-63
lines changed

6 files changed

+84
-63
lines changed

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,8 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
168168
static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm,
169169
int64_t Address, const void *Decoder) {
170170
assert(isUInt<18>(Imm) && "Invalid immediate");
171-
Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Imm << 2)));
171+
Inst.addOperand(
172+
MCOperand::createImm(SignExtend64<20>(Imm << 2) + (Address & 0x3)));
172173
return MCDisassembler::Success;
173174
}
174175

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp‎

Lines changed: 55 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -90,85 +90,103 @@ void XtensaInstPrinter::printMemOperand(const MCInst *MI, int OpNum,
9090
printOperand(MI, OpNum + 1, OS);
9191
}
9292

93-
void XtensaInstPrinter::printBranchTarget(const MCInst *MI, int OpNum,
94-
raw_ostream &OS) {
93+
void XtensaInstPrinter::printBranchTarget(const MCInst *MI, uint64_t Address,
94+
int OpNum, raw_ostream &O) {
9595
const MCOperand &MC = MI->getOperand(OpNum);
9696
if (MI->getOperand(OpNum).isImm()) {
9797
int64_t Val = MC.getImm() + 4;
98-
OS << ". ";
99-
if (Val > 0)
100-
OS << '+';
101-
OS << Val;
98+
printPCRelImm(Address, Val, O);
10299
} else if (MC.isExpr())
103-
MC.getExpr()->print(OS, &MAI);
100+
MC.getExpr()->print(O, &MAI);
104101
else
105102
llvm_unreachable("Invalid operand");
106103
}
107104

108-
void XtensaInstPrinter::printLoopTarget(const MCInst *MI, int OpNum,
109-
raw_ostream &OS) {
105+
void XtensaInstPrinter::printLoopTarget(const MCInst *MI, uint64_t Address,
106+
int OpNum, raw_ostream &O) {
110107
const MCOperand &MC = MI->getOperand(OpNum);
111108
if (MI->getOperand(OpNum).isImm()) {
112109
int64_t Val = MC.getImm() + 4;
113-
OS << ". ";
114-
if (Val > 0)
115-
OS << '+';
116-
OS << Val;
110+
printPCRelImm(Address, Val, O);
117111
} else if (MC.isExpr())
118-
MC.getExpr()->print(OS, &MAI, true);
112+
MC.getExpr()->print(O, &MAI, true);
119113
else
120114
llvm_unreachable("Invalid operand");
121115
}
122116

123-
void XtensaInstPrinter::printJumpTarget(const MCInst *MI, int OpNum,
124-
raw_ostream &OS) {
117+
void XtensaInstPrinter::printJumpTarget(const MCInst *MI, uint64_t Address,
118+
int OpNum, raw_ostream &O) {
125119
const MCOperand &MC = MI->getOperand(OpNum);
126120
if (MC.isImm()) {
127121
int64_t Val = MC.getImm() + 4;
128-
OS << ". ";
129-
if (Val > 0)
130-
OS << '+';
131-
OS << Val;
122+
printPCRelImm(Address, Val, O);
132123
} else if (MC.isExpr())
133-
MC.getExpr()->print(OS, &MAI);
124+
MC.getExpr()->print(O, &MAI);
134125
else
135126
llvm_unreachable("Invalid operand");
136127
;
137128
}
138129

139-
void XtensaInstPrinter::printCallOperand(const MCInst *MI, int OpNum,
140-
raw_ostream &OS) {
130+
void XtensaInstPrinter::printCallOperand(const MCInst *MI, uint64_t Address,
131+
int OpNum, raw_ostream &O) {
141132
const MCOperand &MC = MI->getOperand(OpNum);
142133
if (MC.isImm()) {
143134
int64_t Val = MC.getImm() + 4;
144-
OS << ". ";
145-
if (Val > 0)
146-
OS << '+';
147-
OS << Val;
135+
if (PrintBranchImmAsAddress) {
136+
uint64_t Target = Address;
137+
Target &= ~0x3;
138+
Target += Val & (~0x3);
139+
O << formatHex(Target);
140+
} else {
141+
O << ". ";
142+
if (Val > 0)
143+
O << '+';
144+
O << Val;
145+
}
148146
} else if (MC.isExpr())
149-
MC.getExpr()->print(OS, &MAI);
147+
MC.getExpr()->print(O, &MAI);
150148
else
151149
llvm_unreachable("Invalid operand");
152150
}
153151

154-
void XtensaInstPrinter::printL32RTarget(const MCInst *MI, int OpNum,
155-
raw_ostream &O) {
152+
void XtensaInstPrinter::printL32RTarget(const MCInst *MI, uint64_t Address,
153+
int OpNum, raw_ostream &O) {
156154
const MCOperand &MC = MI->getOperand(OpNum);
157155
if (MC.isImm()) {
158156
int64_t Value = MI->getOperand(OpNum).getImm();
159-
int64_t InstrOff = Value & 0x3;
160-
Value -= InstrOff;
161-
assert((Value >= -262144 && Value <= -4) &&
162-
"Invalid argument, value must be in ranges [-262144,-4]");
163-
Value += ((InstrOff + 0x3) & 0x4) - InstrOff;
164-
O << ". ";
165-
O << Value;
157+
if (PrintBranchImmAsAddress) {
158+
uint64_t Target = (Address + 0x3) & (~0x3);
159+
Value &= ~0x3;
160+
Target += Value;
161+
O << formatHex(Target);
162+
} else {
163+
int64_t InstrOff = Value & 0x3;
164+
Value -= InstrOff;
165+
assert((Value >= -262144 && Value <= -4) &&
166+
"Invalid argument, value must be in ranges [-262144,-4]");
167+
Value += ((InstrOff + 0x3) & 0x4) - InstrOff;
168+
printPCRelImm(Address, Value, O);
169+
}
166170
} else if (MC.isExpr())
167171
MC.getExpr()->print(O, &MAI);
168172
else
169173
llvm_unreachable("Invalid operand");
170174
}
171175

176+
void XtensaInstPrinter::printPCRelImm(uint64_t Address, int64_t Offset,
177+
raw_ostream &O) {
178+
if (PrintBranchImmAsAddress) {
179+
uint64_t Target = Address + Offset;
180+
Target &= 0xffffffff;
181+
O << formatHex(Target);
182+
} else {
183+
O << ". ";
184+
if (Offset > 0)
185+
O << '+';
186+
O << Offset;
187+
}
188+
}
189+
172190
void XtensaInstPrinter::printImm8_AsmOperand(const MCInst *MI, int OpNum,
173191
raw_ostream &O) {
174192
if (MI->getOperand(OpNum).isImm()) {

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -45,11 +45,17 @@ class XtensaInstPrinter : public MCInstPrinter {
4545
// Print various types of operand.
4646
void printOperand(const MCInst *MI, int OpNum, raw_ostream &O);
4747
void printMemOperand(const MCInst *MI, int OpNUm, raw_ostream &O);
48-
void printBranchTarget(const MCInst *MI, int OpNum, raw_ostream &O);
49-
void printLoopTarget(const MCInst *MI, int OpNum, raw_ostream &O);
50-
void printJumpTarget(const MCInst *MI, int OpNum, raw_ostream &O);
51-
void printCallOperand(const MCInst *MI, int OpNum, raw_ostream &O);
52-
void printL32RTarget(const MCInst *MI, int OpNum, raw_ostream &O);
48+
void printBranchTarget(const MCInst *MI, uint64_t Address, int OpNum,
49+
raw_ostream &O);
50+
void printLoopTarget(const MCInst *MI, uint64_t Address, int OpNum,
51+
raw_ostream &O);
52+
void printJumpTarget(const MCInst *MI, uint64_t Address, int OpNum,
53+
raw_ostream &O);
54+
void printCallOperand(const MCInst *MI, uint64_t Address, int OpNum,
55+
raw_ostream &O);
56+
void printL32RTarget(const MCInst *MI, uint64_t Address, int OpNum,
57+
raw_ostream &O);
58+
void printPCRelImm(uint64_t Address, int64_t Offset, raw_ostream &O);
5359

5460
void printImm8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
5561
void printImm8_sh8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);

‎llvm/lib/Target/Xtensa/XtensaOperands.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,32 +222,37 @@ def pcrel32call : Operand<iPTR> {
222222
let EncoderMethod = "getCallEncoding";
223223
let DecoderMethod = "decodeCallOperand";
224224
let ParserMatchClass = XtensaPCRelTargetAsmOperand;
225+
let OperandType = "OPERAND_PCREL";
225226
}
226227

227228
def brtarget : Operand<OtherVT> {
228229
let PrintMethod = "printBranchTarget";
229230
let EncoderMethod = "getBranchTargetEncoding";
230231
let DecoderMethod = "decodeBranchOperand";
231232
let ParserMatchClass = XtensaPCRelTargetAsmOperand;
233+
let OperandType = "OPERAND_PCREL";
232234
}
233235

234236
def jumptarget : Operand<OtherVT> {
235237
let PrintMethod = "printJumpTarget";
236238
let EncoderMethod = "getJumpTargetEncoding";
237239
let DecoderMethod = "decodeJumpOperand";
238240
let ParserMatchClass = XtensaPCRelTargetAsmOperand;
241+
let OperandType = "OPERAND_PCREL";
239242
}
240243

241244
def ltarget : Operand<OtherVT> {
242245
let PrintMethod = "printLoopTarget";
243246
let EncoderMethod = "getLoopTargetEncoding";
244247
let DecoderMethod = "decodeLoopOperand";
245248
let ParserMatchClass = XtensaPCRelTargetAsmOperand;
249+
let OperandType = "OPERAND_PCREL";
246250
}
247251

248252
def L32Rtarget : Operand<i32> {
249253
let PrintMethod = "printL32RTarget";
250254
let EncoderMethod = "getL32RTargetEncoding";
251255
let DecoderMethod = "decodeL32ROperand";
252256
let ParserMatchClass = XtensaPCRelTargetAsmOperand;
257+
let OperandType = "OPERAND_PCREL";
253258
}

‎llvm/lib/Target/Xtensa/XtensaSubtarget.h‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -65,23 +65,14 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
6565
}
6666

6767
bool hasDensity() const { return HasDensity; }
68-
6968
bool hasMAC16() const { return HasMAC16; }
70-
7169
bool hasWindowed() const { return HasWindowed; }
72-
7370
bool hasBoolean() const { return HasBoolean; }
74-
7571
bool hasLoop() const { return HasLoop; }
76-
7772
bool hasSEXT() const { return HasSEXT; }
78-
7973
bool hasCLAMPS() const { return HasCLAMPS; }
80-
8174
bool hasNSA() const { return HasNSA; }
82-
8375
bool hasMINMAX() const { return HasMINMAX; }
84-
8576
bool isWindowedABI() const { return hasWindowed(); }
8677

8778
// Automatically generated by tblgen.

‎llvm/test/MC/Xtensa/Relocations/fixups.s‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -13,43 +13,43 @@ LBL0:
1313

1414
beqz.n a2, LBL1
1515
# CHECK-FIXUP: fixup A - offset: 0, value: LBL1, kind: fixup_xtensa_branch_6
16-
# CHECK-INSTR: beqz.n a2, . +29
16+
# CHECK-INSTR: beqz.n a2, 0x29
1717

1818
beq a0, a1, LBL0
1919
# CHECK-FIXUP: fixup A - offset: 0, value: LBL0, kind:
20-
# CHECK-INSTR: beq a0, a1, . -14
20+
# CHECK-INSTR: beq a0, a1, 0x0
2121

2222
beq a0, a1, LBL1
2323
# CHECK-FIXUP: fixup A - offset: 0, value: LBL1, kind: fixup_xtensa_branch_8
24-
# CHECK-INSTR: beq a0, a1, . +24
24+
# CHECK-INSTR: beq a0, a1, 0x29
2525

2626
beqz a2, LBL0
2727
# CHECK-FIXUP: fixup A - offset: 0, value: LBL0, kind: fixup_xtensa_branch_12
28-
# CHECK-INSTR: beqz a2, . -20
28+
# CHECK-INSTR: beqz a2, 0x0
2929

3030
beqz a2, LBL1
3131
# CHECK-FIXUP: fixup A - offset: 0, value: LBL1, kind: fixup_xtensa_branch_12
32-
# CHECK-INSTR: beqz a2, . +18
32+
# CHECK-INSTR: beqz a2, 0x29
3333

3434
call0 LBL0
3535
# CHECK-FIXUP: fixup A - offset: 0, value: LBL0, kind: fixup_xtensa_call_18
36-
# CHECK-INSTR: call0 . -24
36+
# CHECK-INSTR: call0 0x0
3737

3838
call0 LBL2
3939
# CHECK-FIXUP: fixup A - offset: 0, value: LBL2, kind: fixup_xtensa_call_18
40-
# CHECK-INSTR: call0 . +2068
40+
# CHECK-INSTR: call0 0x830
4141

4242
j LBL0
4343
# CHECK-FIXUP: fixup A - offset: 0, value: LBL0, kind: fixup_xtensa_jump_18
44-
# CHECK-INSTR: j . -32
44+
# CHECK-INSTR: j 0x0
4545

4646
j LBL2
4747
# CHECK-FIXUP: fixup A - offset: 0, value: LBL2, kind: fixup_xtensa_jump_18
48-
# CHECK-INSTR: j . +2061
48+
# CHECK-INSTR: j 0x830
4949

5050
l32r a1, LBL0
5151
# CHECK-FIXUP: fixup A - offset: 0, value: LBL0, kind: fixup_xtensa_l32r_16
52-
# CHECK-INSTR: l32r a1, . -38
52+
# CHECK-INSTR: l32r a1, 0x0
5353

5454
LBL1:
5555

@@ -60,7 +60,7 @@ LBL2:
6060

6161
loop a3, LBL3
6262
# CHECK-FIXUP: fixup A - offset: 0, value: LBL3, kind: fixup_xtensa_loop_8
63-
# CHECK-INSTR: loop a3, . +203
63+
# CHECK-INSTR: loop a3, 0x8fb
6464

6565
.fill 200
6666

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