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s-barannikovs-barannikov
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override everything
1 parent 8eb9135 commit 2f08859

20 files changed

+1196
-1082
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h‎

Lines changed: 323 additions & 271 deletions
Large diffs are not rendered by default.

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h‎

Lines changed: 150 additions & 138 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h‎

Lines changed: 120 additions & 109 deletions
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‎llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h‎

Lines changed: 64 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -52,12 +52,12 @@ class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
5252

5353
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
5454
TTI::UnrollingPreferences &UP,
55-
OptimizationRemarkEmitter *ORE) const;
55+
OptimizationRemarkEmitter *ORE) const override;
5656

5757
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
58-
TTI::PeelingPreferences &PP) const;
58+
TTI::PeelingPreferences &PP) const override;
5959

60-
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const;
60+
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override;
6161
};
6262

6363
class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
@@ -104,78 +104,79 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
104104
public:
105105
explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
106106

107-
bool hasBranchDivergence(const Function *F = nullptr) const;
107+
bool hasBranchDivergence(const Function *F = nullptr) const override;
108108

109109
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
110110
TTI::UnrollingPreferences &UP,
111-
OptimizationRemarkEmitter *ORE) const;
111+
OptimizationRemarkEmitter *ORE) const override;
112112

113113
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
114-
TTI::PeelingPreferences &PP) const;
114+
TTI::PeelingPreferences &PP) const override;
115115

116-
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const {
116+
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override {
117117
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
118118
return TTI::PSK_FastHardware;
119119
}
120120

121-
unsigned getNumberOfRegisters(unsigned RCID) const;
122-
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
123-
unsigned getMinVectorRegisterBitWidth() const;
124-
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
121+
unsigned getNumberOfRegisters(unsigned RCID) const override;
122+
TypeSize
123+
getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
124+
unsigned getMinVectorRegisterBitWidth() const override;
125+
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override;
125126
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
126127
unsigned ChainSizeInBytes,
127-
VectorType *VecTy) const;
128+
VectorType *VecTy) const override;
128129
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
129130
unsigned ChainSizeInBytes,
130-
VectorType *VecTy) const;
131-
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
131+
VectorType *VecTy) const override;
132+
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;
132133

133134
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
134135
unsigned AddrSpace) const;
135136
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
136-
unsigned AddrSpace) const;
137+
unsigned AddrSpace) const override;
137138
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
138-
unsigned AddrSpace) const;
139+
unsigned AddrSpace) const override;
139140

140-
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const;
141-
Type *
142-
getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
143-
unsigned SrcAddrSpace, unsigned DestAddrSpace,
144-
Align SrcAlign, Align DestAlign,
145-
std::optional<uint32_t> AtomicElementSize) const;
141+
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override;
142+
Type *getMemcpyLoopLoweringType(
143+
LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
144+
unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
145+
std::optional<uint32_t> AtomicElementSize) const override;
146146

147147
void getMemcpyLoopResidualLoweringType(
148148
SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
149149
unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
150150
Align SrcAlign, Align DestAlign,
151-
std::optional<uint32_t> AtomicCpySize) const;
152-
unsigned getMaxInterleaveFactor(ElementCount VF) const;
151+
std::optional<uint32_t> AtomicCpySize) const override;
152+
unsigned getMaxInterleaveFactor(ElementCount VF) const override;
153153

154-
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const;
154+
bool getTgtMemIntrinsic(IntrinsicInst *Inst,
155+
MemIntrinsicInfo &Info) const override;
155156

156157
InstructionCost getArithmeticInstrCost(
157158
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
158159
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
159160
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
160161
ArrayRef<const Value *> Args = {},
161-
const Instruction *CxtI = nullptr) const;
162+
const Instruction *CxtI = nullptr) const override;
162163

163164
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
164-
const Instruction *I = nullptr) const;
165+
const Instruction *I = nullptr) const override;
165166

166167
bool isInlineAsmSourceOfDivergence(const CallInst *CI,
167168
ArrayRef<unsigned> Indices = {}) const;
168169

169170
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
170171
TTI::TargetCostKind CostKind,
171172
unsigned Index, Value *Op0,
172-
Value *Op1) const;
173+
Value *Op1) const override;
173174

174175
bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const;
175-
bool isSourceOfDivergence(const Value *V) const;
176-
bool isAlwaysUniform(const Value *V) const;
176+
bool isSourceOfDivergence(const Value *V) const override;
177+
bool isAlwaysUniform(const Value *V) const override;
177178

178-
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
179+
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override {
179180
// Address space casts must cast between different address spaces.
180181
if (FromAS == ToAS)
181182
return false;
@@ -196,11 +197,11 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
196197
return false;
197198
}
198199

199-
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const {
200+
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override {
200201
return AMDGPU::addrspacesMayAlias(AS0, AS1);
201202
}
202203

203-
unsigned getFlatAddressSpace() const {
204+
unsigned getFlatAddressSpace() const override {
204205
// Don't bother running InferAddressSpaces pass on graphics shaders which
205206
// don't use flat addressing.
206207
if (IsGraphics)
@@ -209,24 +210,25 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
209210
}
210211

211212
bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
212-
Intrinsic::ID IID) const;
213+
Intrinsic::ID IID) const override;
213214

214-
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const {
215+
bool
216+
canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override {
215217
return AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS &&
216218
AS != AMDGPUAS::PRIVATE_ADDRESS;
217219
}
218220

219221
Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
220-
Value *NewV) const;
222+
Value *NewV) const override;
221223

222224
bool canSimplifyLegacyMulToMul(const Instruction &I, const Value *Op0,
223225
const Value *Op1, InstCombiner &IC) const;
224226

225227
bool simplifyDemandedLaneMaskArg(InstCombiner &IC, IntrinsicInst &II,
226228
unsigned LaneAgIdx) const;
227229

228-
std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
229-
IntrinsicInst &II) const;
230+
std::optional<Instruction *>
231+
instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override;
230232

231233
Value *simplifyAMDGCNLaneIntrinsicDemanded(InstCombiner &IC,
232234
IntrinsicInst &II,
@@ -237,40 +239,43 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
237239
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
238240
APInt &UndefElts2, APInt &UndefElts3,
239241
std::function<void(Instruction *, unsigned, APInt, APInt &)>
240-
SimplifyAndSetOp) const;
242+
SimplifyAndSetOp) const override;
241243

242244
InstructionCost getVectorSplitCost() const { return 0; }
243245

244-
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
245-
ArrayRef<int> Mask,
246-
TTI::TargetCostKind CostKind, int Index,
247-
VectorType *SubTp,
248-
ArrayRef<const Value *> Args = {},
249-
const Instruction *CxtI = nullptr) const;
246+
InstructionCost
247+
getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef<int> Mask,
248+
TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,
249+
ArrayRef<const Value *> Args = {},
250+
const Instruction *CxtI = nullptr) const override;
250251

251252
bool isProfitableToSinkOperands(Instruction *I,
252-
SmallVectorImpl<Use *> &Ops) const;
253+
SmallVectorImpl<Use *> &Ops) const override;
253254

254255
bool areInlineCompatible(const Function *Caller,
255-
const Function *Callee) const;
256+
const Function *Callee) const override;
256257

257-
int getInliningLastCallToStaticBonus() const;
258-
unsigned getInliningThresholdMultiplier() const { return 11; }
259-
unsigned adjustInliningThreshold(const CallBase *CB) const;
260-
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const;
258+
int getInliningLastCallToStaticBonus() const override;
259+
unsigned getInliningThresholdMultiplier() const override { return 11; }
260+
unsigned adjustInliningThreshold(const CallBase *CB) const override;
261+
unsigned getCallerAllocaCost(const CallBase *CB,
262+
const AllocaInst *AI) const override;
261263

262-
int getInlinerVectorBonusPercent() const { return InlinerVectorBonusPercent; }
264+
int getInlinerVectorBonusPercent() const override {
265+
return InlinerVectorBonusPercent;
266+
}
263267

264268
InstructionCost
265269
getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
266270
std::optional<FastMathFlags> FMF,
267-
TTI::TargetCostKind CostKind) const;
271+
TTI::TargetCostKind CostKind) const override;
268272

269-
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
270-
TTI::TargetCostKind CostKind) const;
271-
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
272-
FastMathFlags FMF,
273-
TTI::TargetCostKind CostKind) const;
273+
InstructionCost
274+
getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
275+
TTI::TargetCostKind CostKind) const override;
276+
InstructionCost
277+
getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
278+
TTI::TargetCostKind CostKind) const override;
274279

275280
/// Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.
276281
unsigned getCacheLineSize() const override { return 128; }
@@ -283,7 +288,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
283288
bool shouldPrefetchAddressSpace(unsigned AS) const override;
284289
void collectKernelLaunchBounds(
285290
const Function &F,
286-
SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const;
291+
SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const override;
287292
};
288293

289294
} // end namespace llvm

‎llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h‎

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -43,27 +43,28 @@ class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
4343

4444
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
4545
TTI::UnrollingPreferences &UP,
46-
OptimizationRemarkEmitter *ORE) const;
46+
OptimizationRemarkEmitter *ORE) const override;
4747
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
48-
TTI::PeelingPreferences &PP) const;
48+
TTI::PeelingPreferences &PP) const override;
4949
unsigned getHardwareNumberOfRegisters(bool Vec) const;
50-
unsigned getNumberOfRegisters(unsigned ClassID) const;
51-
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
52-
unsigned getMinVectorRegisterBitWidth() const;
53-
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
50+
unsigned getNumberOfRegisters(unsigned ClassID) const override;
51+
TypeSize
52+
getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
53+
unsigned getMinVectorRegisterBitWidth() const override;
54+
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;
5455
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
5556
unsigned AddrSpace) const;
5657
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
57-
unsigned AddrSpace) const;
58+
unsigned AddrSpace) const override;
5859
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
59-
unsigned AddrSpace) const;
60-
unsigned getMaxInterleaveFactor(ElementCount VF) const;
60+
unsigned AddrSpace) const override;
61+
unsigned getMaxInterleaveFactor(ElementCount VF) const override;
6162
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
62-
const Instruction *I = nullptr) const;
63+
const Instruction *I = nullptr) const override;
6364
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
6465
TTI::TargetCostKind CostKind,
6566
unsigned Index, Value *Op0,
66-
Value *Op1) const;
67+
Value *Op1) const override;
6768
};
6869

6970
} // end namespace llvm

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