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[GISel] Make assignValueToReg take CCValAssign by const reference. (#70086)
This was previously passed by value. It used to be passed by non-const reference, but it was changed to value in D110610. I'm not sure why.
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12 files changed

+36
-37
lines changed

12 files changed

+36
-37
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ class CallLowering {
268268
/// handle the appropriate COPY (either to or from) and mark any
269269
/// relevant uses/defines as needed.
270270
virtual void assignValueToReg(Register ValVReg, Register PhysReg,
271-
CCValAssign VA) = 0;
271+
const CCValAssign &VA) = 0;
272272

273273
/// The specified value has been assigned to a stack
274274
/// location. Load or store it there, with appropriate extension
@@ -323,11 +323,12 @@ class CallLowering {
323323

324324
/// Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on \p
325325
/// VA, returning the new register if a hint was inserted.
326-
Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
326+
Register buildExtensionHint(const CCValAssign &VA, Register SrcReg,
327+
LLT NarrowTy);
327328

328329
/// Provides a default implementation for argument handling.
329330
void assignValueToReg(Register ValVReg, Register PhysReg,
330-
CCValAssign VA) override;
331+
const CCValAssign &VA) override;
331332
};
332333

333334
/// Base class for ValueHandlers used for arguments passed to a function call,

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1184,9 +1184,8 @@ Register CallLowering::ValueHandler::extendRegister(Register ValReg,
11841184

11851185
void CallLowering::ValueAssigner::anchor() {}
11861186

1187-
Register CallLowering::IncomingValueHandler::buildExtensionHint(CCValAssign &VA,
1188-
Register SrcReg,
1189-
LLT NarrowTy) {
1187+
Register CallLowering::IncomingValueHandler::buildExtensionHint(
1188+
const CCValAssign &VA, Register SrcReg, LLT NarrowTy) {
11901189
switch (VA.getLocInfo()) {
11911190
case CCValAssign::LocInfo::ZExt: {
11921191
return MIRBuilder
@@ -1226,9 +1225,8 @@ static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) {
12261225
(DstTy.isPointer() && SrcTy.isScalar());
12271226
}
12281227

1229-
void CallLowering::IncomingValueHandler::assignValueToReg(Register ValVReg,
1230-
Register PhysReg,
1231-
CCValAssign VA) {
1228+
void CallLowering::IncomingValueHandler::assignValueToReg(
1229+
Register ValVReg, Register PhysReg, const CCValAssign &VA) {
12321230
const MVT LocVT = VA.getLocVT();
12331231
const LLT LocTy(LocVT);
12341232
const LLT RegTy = MRI.getType(ValVReg);

‎llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,7 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
158158
}
159159

160160
void assignValueToReg(Register ValVReg, Register PhysReg,
161-
CCValAssign VA) override {
161+
const CCValAssign &VA) override {
162162
markPhysRegUsed(PhysReg);
163163
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
164164
}
@@ -284,7 +284,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
284284
}
285285

286286
void assignValueToReg(Register ValVReg, Register PhysReg,
287-
CCValAssign VA) override {
287+
const CCValAssign &VA) override {
288288
MIB.addUse(PhysReg, RegState::Implicit);
289289
Register ExtReg = extendRegister(ValVReg, VA);
290290
MIRBuilder.buildCopy(PhysReg, ExtReg);

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
6262
}
6363

6464
void assignValueToReg(Register ValVReg, Register PhysReg,
65-
CCValAssign VA) override {
65+
const CCValAssign &VA) override {
6666
Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
6767

6868
// If this is a scalar return, insert a readfirstlane just in case the value
@@ -118,7 +118,7 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
118118
}
119119

120120
void assignValueToReg(Register ValVReg, Register PhysReg,
121-
CCValAssign VA) override {
121+
const CCValAssign &VA) override {
122122
markPhysRegUsed(PhysReg);
123123

124124
if (VA.getLocVT().getSizeInBits() < 32) {
@@ -231,7 +231,7 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
231231
}
232232

233233
void assignValueToReg(Register ValVReg, Register PhysReg,
234-
CCValAssign VA) override {
234+
const CCValAssign &VA) override {
235235
MIB.addUse(PhysReg, RegState::Implicit);
236236
Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
237237
MIRBuilder.buildCopy(PhysReg, ExtReg);

‎llvm/lib/Target/ARM/ARMCallLowering.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
110110
}
111111

112112
void assignValueToReg(Register ValVReg, Register PhysReg,
113-
CCValAssign VA) override {
113+
const CCValAssign &VA) override {
114114
assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
115115
assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
116116

@@ -136,14 +136,14 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
136136
std::function<void()> *Thunk) override {
137137
assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
138138

139-
CCValAssign VA = VAs[0];
139+
const CCValAssign &VA = VAs[0];
140140
assert(VA.needsCustom() && "Value doesn't need custom handling");
141141

142142
// Custom lowering for other types, such as f16, is currently not supported
143143
if (VA.getValVT() != MVT::f64)
144144
return 0;
145145

146-
CCValAssign NextVA = VAs[1];
146+
const CCValAssign &NextVA = VAs[1];
147147
assert(NextVA.needsCustom() && "Value doesn't need custom handling");
148148
assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
149149

@@ -283,7 +283,7 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
283283
}
284284

285285
void assignValueToReg(Register ValVReg, Register PhysReg,
286-
CCValAssign VA) override {
286+
const CCValAssign &VA) override {
287287
assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
288288
assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
289289

@@ -312,14 +312,14 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
312312
std::function<void()> *Thunk) override {
313313
assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
314314

315-
CCValAssign VA = VAs[0];
315+
const CCValAssign &VA = VAs[0];
316316
assert(VA.needsCustom() && "Value doesn't need custom handling");
317317

318318
// Custom lowering for other types, such as f16, is currently not supported
319319
if (VA.getValVT() != MVT::f64)
320320
return 0;
321321

322-
CCValAssign NextVA = VAs[1];
322+
const CCValAssign &NextVA = VAs[1];
323323
assert(NextVA.needsCustom() && "Value doesn't need custom handling");
324324
assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
325325

‎llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ struct M68kOutgoingArgHandler : public CallLowering::OutgoingValueHandler {
3636
STI(MIRBuilder.getMF().getSubtarget<M68kSubtarget>()) {}
3737

3838
void assignValueToReg(Register ValVReg, Register PhysReg,
39-
CCValAssign VA) override {
39+
const CCValAssign &VA) override {
4040
MIB.addUse(PhysReg, RegState::Implicit);
4141
Register ExtReg = extendRegister(ValVReg, VA);
4242
MIRBuilder.buildCopy(PhysReg, ExtReg);
@@ -127,7 +127,7 @@ bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
127127

128128
void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
129129
Register PhysReg,
130-
CCValAssign VA) {
130+
const CCValAssign &VA) {
131131
MIRBuilder.getMRI()->addLiveIn(PhysReg);
132132
MIRBuilder.getMBB().addLiveIn(PhysReg);
133133
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
@@ -160,7 +160,7 @@ Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
160160
}
161161

162162
void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg,
163-
CCValAssign VA) {
163+
const CCValAssign &VA) {
164164
MIB.addDef(PhysReg, RegState::Implicit);
165165
MIRBuilder.buildCopy(ValVReg, PhysReg);
166166
}

‎llvm/lib/Target/M68k/GISel/M68kCallLowering.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
5353

5454
private:
5555
void assignValueToReg(Register ValVReg, Register PhysReg,
56-
CCValAssign VA) override;
56+
const CCValAssign &VA) override;
5757

5858
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
5959
const MachinePointerInfo &MPO,
@@ -76,7 +76,7 @@ struct CallReturnHandler : public M68kIncomingValueHandler {
7676

7777
private:
7878
void assignValueToReg(Register ValVReg, Register PhysReg,
79-
CCValAssign VA) override;
79+
const CCValAssign &VA) override;
8080

8181
MachineInstrBuilder &MIB;
8282
};

‎llvm/lib/Target/Mips/MipsCallLowering.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ class MipsIncomingValueHandler : public CallLowering::IncomingValueHandler {
9393

9494
private:
9595
void assignValueToReg(Register ValVReg, Register PhysReg,
96-
CCValAssign VA) override;
96+
const CCValAssign &VA) override;
9797

9898
Register getStackAddress(uint64_t Size, int64_t Offset,
9999
MachinePointerInfo &MPO,
@@ -130,7 +130,7 @@ class CallReturnHandler : public MipsIncomingValueHandler {
130130

131131
void MipsIncomingValueHandler::assignValueToReg(Register ValVReg,
132132
Register PhysReg,
133-
CCValAssign VA) {
133+
const CCValAssign &VA) {
134134
markPhysRegUsed(PhysReg);
135135
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
136136
}
@@ -200,7 +200,7 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
200200

201201
private:
202202
void assignValueToReg(Register ValVReg, Register PhysReg,
203-
CCValAssign VA) override;
203+
const CCValAssign &VA) override;
204204

205205
Register getStackAddress(uint64_t Size, int64_t Offset,
206206
MachinePointerInfo &MPO,
@@ -219,7 +219,7 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
219219

220220
void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg,
221221
Register PhysReg,
222-
CCValAssign VA) {
222+
const CCValAssign &VA) {
223223
Register ExtReg = extendRegister(ValVReg, VA);
224224
MIRBuilder.buildCopy(PhysReg, ExtReg);
225225
MIB.addUse(PhysReg, RegState::Implicit);

‎llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
3636
: OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
3737

3838
void assignValueToReg(Register ValVReg, Register PhysReg,
39-
CCValAssign VA) override;
39+
const CCValAssign &VA) override;
4040
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
4141
const MachinePointerInfo &MPO,
4242
const CCValAssign &VA) override;
@@ -49,7 +49,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
4949
} // namespace
5050

5151
void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,
52-
CCValAssign VA) {
52+
const CCValAssign &VA) {
5353
MIB.addUse(PhysReg, RegState::Implicit);
5454
Register ExtReg = extendRegister(ValVReg, VA);
5555
MIRBuilder.buildCopy(PhysReg, ExtReg);
@@ -144,7 +144,7 @@ bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
144144

145145
void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
146146
Register PhysReg,
147-
CCValAssign VA) {
147+
const CCValAssign &VA) {
148148
markPhysRegUsed(PhysReg);
149149
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
150150
}

‎llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ class PPCIncomingValueHandler : public CallLowering::IncomingValueHandler {
4646

4747
private:
4848
void assignValueToReg(Register ValVReg, Register PhysReg,
49-
CCValAssign VA) override;
49+
const CCValAssign &VA) override;
5050

5151
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
5252
const MachinePointerInfo &MPO,

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