Address Roland's concern that XXMTACC/XXMFACC are awkward and probably

not handled properly. They have been superseded by new instructions that
can do the same thing, so we don't actually want to create them.

Author: lei137

llvm/lib/Target/PowerPC/PPCInstrMMA.td

@@ -535,25 +535,25 @@ let Predicates = [MMA, IsNotISAFuture] in {
 }
 
 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
+  // For Future and up XXMFACCW and XXMTACCW will not have patterns.
   // On Future CPU the wacc registers no longer overlap with the vsr registers
-  // so register allocation need to match 4 vsr registers with one wacc
-  // register. XXMTACC/XXFACC will be aliased to these new instructions.
-  def DMXXMFACC:
-    XForm_AT3<31, 0, 177, (outs wacc:$ATo), (ins wacc:$AT), "dmxxmfacc $AT",
-              IIC_VecGeneral,
-              [(set v512i1:$ATo, (int_ppc_mma_xxmfacc v512i1:$AT))]>,
+  // and so register allocation would have to know to match 4 vsr registers
+  // with one wacc register.
+  // On top of that Future CPU has a more convenient way to move between vsrs
+  // and wacc registers using xxextfdmr512 and xxinstdmr512.
+  def XXMFACCW :
+    XForm_AT3<31, 0, 177, (outs wacc:$ATo), (ins wacc:$AT), "xxmfacc $AT",
+              IIC_VecGeneral, []>,
               RegConstraint<"$ATo = $AT">, NoEncode<"$ATo">;
-  def DMXXMTACC:
-    XForm_AT3<31, 1, 177, (outs wacc:$AT), (ins wacc:$ATi), "dmxxmtacc $AT",
-              IIC_VecGeneral,
-              [(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>,
+  def XXMTACCW :
+    XForm_AT3<31, 1, 177, (outs wacc:$AT), (ins wacc:$ATi), "xxmtacc $AT",
+              IIC_VecGeneral, []>,
               RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
 
   let isAsCheapAsAMove = 1, isReMaterializable = 1 in {
-    def DMXXSETACCZ:
+    def DMXXSETACCZ :
       XForm_AT3<31, 3, 177, (outs wacc:$AT), (ins), "dmxxsetaccz $AT",
-                IIC_VecGeneral,
-                [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>;
+                IIC_VecGeneral, [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>;
   }
 
   def XVI8GER4WSPP :

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

@@ -20,8 +20,6 @@ def sub_64 : SubRegIndex<64>;
 def sub_64_hi_phony : SubRegIndex<64,64>;
 def sub_vsx0 : SubRegIndex<128>;
 def sub_vsx1 : SubRegIndex<128, 128>;
-def sub_vsx2 : ComposedSubRegIndex<sub_vsx1, sub_vsx0>;
-def sub_vsx3 : ComposedSubRegIndex<sub_vsx2, sub_vsx0>;
 def sub_gp8_x0 : SubRegIndex<64>;
 def sub_gp8_x1 : SubRegIndex<64, 64>;
 def sub_fp0 : SubRegIndex<64>;

llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir

@@ -6,17 +6,17 @@
 # Keep track of all of the lanemasks for various subregsiters.
 #
 # CHECK: %3 [80r,80d:0) 0@80r  L000000000000000C [80r,80d:0) 0@80r  weight:0.000000e+00
-# CHECK: %4 [96r,96d:0) 0@96r  L0000000000007000 [96r,96d:0) 0@96r  weight:0.000000e+00
+# CHECK: %4 [96r,96d:0) 0@96r  L0000000000003000 [96r,96d:0) 0@96r  weight:0.000000e+00
 # CHECK: %5 [112r,112d:0) 0@112r  L000000000000000C [112r,112d:0) 0@112r  weight:0.000000e+00
-# CHECK: %6 [128r,128d:0) 0@128r  L0000000000007000 [128r,128d:0) 0@128r  weight:0.000000e+00
+# CHECK: %6 [128r,128d:0) 0@128r  L0000000000003000 [128r,128d:0) 0@128r  weight:0.000000e+00
 # CHECK: %7 [144r,144d:0) 0@144r  L0000000000000004 [144r,144d:0) 0@144r  weight:0.000000e+00
-# CHECK: %8 [160r,160d:0) 0@160r  L0000000000002000 [160r,160d:0) 0@160r  weight:0.000000e+00
+# CHECK: %8 [160r,160d:0) 0@160r  L0000000000001000 [160r,160d:0) 0@160r  weight:0.000000e+00
 # CHECK: %9 [176r,176d:0) 0@176r  L0000000000000004 [176r,176d:0) 0@176r  weight:0.000000e+00
-# CHECK: %10 [192r,192d:0) 0@192r  L0000000000002000 [192r,192d:0) 0@192r  weight:0.000000e+00
-# CHECK: %11 [208r,208d:0) 0@208r  L0000000000008000 [208r,208d:0) 0@208r  weight:0.000000e+00
-# CHECK: %12 [224r,224d:0) 0@224r  L0000000000020000 [224r,224d:0) 0@224r  weight:0.000000e+00
-# CHECK: %13 [240r,240d:0) 0@240r  L000000000000700C [240r,240d:0) 0@240r  weight:0.000000e+00
-# CHECK: %14 [256r,256d:0) 0@256r  L0000000000078000 [256r,256d:0) 0@256r  weight:0.000000e+00
+# CHECK: %10 [192r,192d:0) 0@192r  L0000000000001000 [192r,192d:0) 0@192r  weight:0.000000e+00
+# CHECK: %11 [208r,208d:0) 0@208r  L0000000000004000 [208r,208d:0) 0@208r  weight:0.000000e+00
+# CHECK: %12 [224r,224d:0) 0@224r  L0000000000010000 [224r,224d:0) 0@224r  weight:0.000000e+00
+# CHECK: %13 [240r,240d:0) 0@240r  L000000000000300C [240r,240d:0) 0@240r  weight:0.000000e+00
+# CHECK: %14 [256r,256d:0) 0@256r  L000000000003C000 [256r,256d:0) 0@256r  weight:0.000000e+00
 
 
 # CHECK:       0B bb.0