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[AMDGPU] Elide bitcast combine to build_vector in case i64 constant can be materialized
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6 files changed

+73
-35
lines changed

6 files changed

+73
-35
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5296,6 +5296,13 @@ SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
52965296
return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
52975297
}
52985298

5299+
bool AMDGPUTargetLowering::canMov64bImm(uint64_t Val, SelectionDAG &DAG) const {
5300+
if (!Subtarget->isGCN())
5301+
return false;
5302+
auto &ST = DAG.getSubtarget<GCNSubtarget>();
5303+
return ST.hasMovB64() && (ST.has64BitLiterals() || isUInt<32>(Val));
5304+
}
5305+
52995306
SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
53005307
DAGCombinerInfo &DCI) const {
53015308
SelectionDAG &DAG = DCI.DAG;
@@ -5346,6 +5353,8 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
53465353
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
53475354
SDLoc SL(N);
53485355
uint64_t CVal = C->getZExtValue();
5356+
if (canMov64bImm(CVal, DAG))
5357+
break;
53495358
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
53505359
DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
53515360
DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
@@ -5356,6 +5365,8 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
53565365
const APInt &Val = C->getValueAPF().bitcastToAPInt();
53575366
SDLoc SL(N);
53585367
uint64_t CVal = Val.getZExtValue();
5368+
if (canMov64bImm(CVal, DAG))
5369+
break;
53595370
SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
53605371
DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
53615372
DAG.getConstant(Hi_32(CVal), SL, MVT::i32));

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,9 @@ class AMDGPUTargetLowering : public TargetLowering {
103103
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
104104

105105
protected:
106+
/// Check whether value Val can be supported by v_mov_b64, for the current
107+
/// target.
108+
bool canMov64bImm(uint64_t Val, SelectionDAG &DAG) const;
106109
bool shouldCombineMemoryType(EVT VT) const;
107110
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
108111
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14584,13 +14584,39 @@ SITargetLowering::performExtractVectorEltCombine(SDNode *N,
1458414584
return V;
1458514585
}
1458614586

14587+
// EXTRACT_VECTOR_ELT (v2i32 bitcast (i64/f64:k), Idx)
14588+
// =>
14589+
// i32:Lo(k) if Idx == 0, or
14590+
// i32:Hi(k) if Idx == 1
14591+
auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
14592+
if (Vec.getOpcode() == ISD::BITCAST && VecVT == MVT::v2i32 && Idx) {
14593+
SDLoc SL(N);
14594+
SDValue PeekThrough = peekThroughBitcasts(Vec);
14595+
auto *KImm = dyn_cast<ConstantSDNode>(PeekThrough);
14596+
if (KImm && KImm->getValueType(0).getSizeInBits() == 64) {
14597+
uint64_t KImmValue = KImm->getZExtValue();
14598+
if (Idx->getZExtValue() == 0)
14599+
return DAG.getConstant(Lo_32(KImmValue), SL, MVT::i32);
14600+
else
14601+
return DAG.getConstant(Hi_32(KImmValue), SL, MVT::i32);
14602+
}
14603+
auto *KFPImm = dyn_cast<ConstantFPSDNode>(PeekThrough);
14604+
if (KFPImm && KFPImm->getValueType(0).getSizeInBits() == 64) {
14605+
uint64_t KFPImmValue =
14606+
KFPImm->getValueAPF().bitcastToAPInt().getZExtValue();
14607+
if (Idx->getZExtValue() == 0)
14608+
return DAG.getConstant(Lo_32(KFPImmValue), SL, MVT::i32);
14609+
else
14610+
return DAG.getConstant(Hi_32(KFPImmValue), SL, MVT::i32);
14611+
}
14612+
}
14613+
1458714614
if (!DCI.isBeforeLegalize())
1458814615
return SDValue();
1458914616

1459014617
// Try to turn sub-dword accesses of vectors into accesses of the same 32-bit
1459114618
// elements. This exposes more load reduction opportunities by replacing
1459214619
// multiple small extract_vector_elements with a single 32-bit extract.
14593-
auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
1459414620
if (isa<MemSDNode>(Vec) && VecEltSize <= 16 && VecEltVT.isByteSized() &&
1459514621
VecSize > 32 && VecSize % 32 == 0 && Idx) {
1459614622
EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT);

‎llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll‎

Lines changed: 29 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -7,21 +7,18 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
77
; CHECK-NEXT: s_load_dword s0, s[4:5], 0x8
88
; CHECK-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x0
99
; CHECK-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
10-
; CHECK-NEXT: v_mov_b32_e32 v1, 0x3e21eeb6
11-
; CHECK-NEXT: v_mov_b32_e32 v20, 0
10+
; CHECK-NEXT: v_mov_b32_e32 v30, 0x9037ab78
11+
; CHECK-NEXT: v_mov_b32_e32 v31, 0x3e21eeb6
1212
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
1313
; CHECK-NEXT: s_bitcmp1_b32 s0, 0
1414
; CHECK-NEXT: s_cselect_b64 s[16:17], -1, 0
1515
; CHECK-NEXT: s_xor_b64 s[18:19], s[16:17], -1
1616
; CHECK-NEXT: s_bitcmp1_b32 s0, 8
1717
; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0
1818
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]
19-
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
20-
; CHECK-NEXT: v_mov_b32_e32 v0, 0x9037ab78
21-
; CHECK-NEXT: v_accvgpr_write_b32 a3, v1
2219
; CHECK-NEXT: s_xor_b64 s[20:21], s[2:3], -1
20+
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
2321
; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
24-
; CHECK-NEXT: v_accvgpr_write_b32 a2, v0
2522
; CHECK-NEXT: v_mov_b32_e32 v2, 0xa17f65f6
2623
; CHECK-NEXT: v_mov_b32_e32 v3, 0xbe927e4f
2724
; CHECK-NEXT: v_mov_b32_e32 v4, 0x19f4ec90
@@ -37,14 +34,15 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
3734
; CHECK-NEXT: v_mov_b32_e32 v14, 0x8427b883
3835
; CHECK-NEXT: v_mov_b32_e32 v15, 0x3fae1bb4
3936
; CHECK-NEXT: s_mov_b64 s[22:23], 0
40-
; CHECK-NEXT: v_mov_b32_e32 v0, 0x57b87036
41-
; CHECK-NEXT: v_mov_b32_e32 v1, 0x3fb3b136
37+
; CHECK-NEXT: v_mov_b32_e32 v20, 0x57b87036
38+
; CHECK-NEXT: v_mov_b32_e32 v21, 0x3fb3b136
4239
; CHECK-NEXT: s_and_b64 s[4:5], exec, s[16:17]
4340
; CHECK-NEXT: v_mov_b32_e32 v18, 0x55555523
4441
; CHECK-NEXT: v_mov_b32_e32 v19, 0xbfd55555
4542
; CHECK-NEXT: s_and_b64 s[6:7], exec, s[18:19]
46-
; CHECK-NEXT: v_mov_b32_e32 v21, v20
47-
; CHECK-NEXT: ; implicit-def: $vgpr30_vgpr31
43+
; CHECK-NEXT: v_mov_b32_e32 v0, 0
44+
; CHECK-NEXT: v_mov_b64_e32 v[16:17], 0
45+
; CHECK-NEXT: ; implicit-def: $agpr0_agpr1
4846
; CHECK-NEXT: ; implicit-def: $vgpr22_vgpr23
4947
; CHECK-NEXT: s_branch .LBB0_2
5048
; CHECK-NEXT: .LBB0_1: ; %Flow9
@@ -64,12 +62,11 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
6462
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
6563
; CHECK-NEXT: v_mov_b64_e32 v[24:25], s[14:15]
6664
; CHECK-NEXT: flat_load_dwordx2 v[24:25], v[24:25]
67-
; CHECK-NEXT: v_accvgpr_read_b32 v27, a3
68-
; CHECK-NEXT: v_accvgpr_read_b32 v26, a2
65+
; CHECK-NEXT: v_mov_b64_e32 v[26:27], v[30:31]
6966
; CHECK-NEXT: v_mov_b64_e32 v[28:29], v[2:3]
70-
; CHECK-NEXT: v_mov_b64_e32 v[16:17], v[0:1]
71-
; CHECK-NEXT: v_accvgpr_write_b32 a0, 0
72-
; CHECK-NEXT: v_accvgpr_write_b32 a1, 0
67+
; CHECK-NEXT: v_mov_b64_e32 v[16:17], v[20:21]
68+
; CHECK-NEXT: v_accvgpr_write_b32 a2, 0
69+
; CHECK-NEXT: v_accvgpr_write_b32 a3, 0
7370
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
7471
; CHECK-NEXT: v_fmac_f64_e32 v[26:27], 0, v[24:25]
7572
; CHECK-NEXT: v_fmac_f64_e32 v[28:29], 0, v[26:27]
@@ -96,30 +93,32 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
9693
; CHECK-NEXT: .LBB0_6: ; %.preheader1855.i.i.i3329
9794
; CHECK-NEXT: ; Parent Loop BB0_2 Depth=1
9895
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
99-
; CHECK-NEXT: v_accvgpr_read_b32 v29, a1
100-
; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
96+
; CHECK-NEXT: v_accvgpr_read_b32 v29, a3
97+
; CHECK-NEXT: v_accvgpr_read_b32 v28, a2
10198
; CHECK-NEXT: s_mov_b64 s[24:25], -1
10299
; CHECK-NEXT: s_mov_b64 s[8:9], -1
103100
; CHECK-NEXT: s_mov_b64 vcc, s[2:3]
104-
; CHECK-NEXT: ; implicit-def: $agpr0_agpr1
101+
; CHECK-NEXT: ; implicit-def: $agpr2_agpr3
105102
; CHECK-NEXT: s_cbranch_vccz .LBB0_5
106103
; CHECK-NEXT: ; %bb.7: ; %.lr.ph2070.i.i.i3291
107104
; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2
108-
; CHECK-NEXT: v_accvgpr_write_b32 a0, v30
109-
; CHECK-NEXT: v_accvgpr_write_b32 a1, v31
105+
; CHECK-NEXT: v_accvgpr_mov_b32 a3, a1
106+
; CHECK-NEXT: v_accvgpr_mov_b32 a2, a0
110107
; CHECK-NEXT: s_mov_b64 s[8:9], s[18:19]
111108
; CHECK-NEXT: s_mov_b64 vcc, s[6:7]
112109
; CHECK-NEXT: s_cbranch_vccz .LBB0_5
113110
; CHECK-NEXT: ; %bb.8: ; %.preheader1856.preheader.i.i.i3325
114111
; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2
115-
; CHECK-NEXT: v_accvgpr_write_b32 a0, v26
112+
; CHECK-NEXT: v_accvgpr_write_b32 a2, v26
116113
; CHECK-NEXT: s_mov_b64 s[24:25], 0
117-
; CHECK-NEXT: v_accvgpr_write_b32 a1, v27
114+
; CHECK-NEXT: v_accvgpr_write_b32 a3, v27
118115
; CHECK-NEXT: s_mov_b64 s[8:9], 0
119116
; CHECK-NEXT: s_branch .LBB0_5
120117
; CHECK-NEXT: .LBB0_9: ; in Loop: Header=BB0_2 Depth=1
118+
; CHECK-NEXT: v_mov_b64_e32 v[24:25], s[10:11]
119+
; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
121120
; CHECK-NEXT: s_mov_b64 s[22:23], 0
122-
; CHECK-NEXT: v_mov_b64_e32 v[30:31], s[10:11]
121+
; CHECK-NEXT: v_accvgpr_write_b32 a1, v25
123122
; CHECK-NEXT: s_mov_b64 s[8:9], s[20:21]
124123
; CHECK-NEXT: s_branch .LBB0_15
125124
; CHECK-NEXT: .LBB0_10: ; in Loop: Header=BB0_2 Depth=1
@@ -136,19 +135,21 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
136135
; CHECK-NEXT: v_cndmask_b32_e64 v23, v23, 0, s[16:17]
137136
; CHECK-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[16:17]
138137
; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[8:9]
139-
; CHECK-NEXT: v_mov_b32_e32 v17, v16
140138
; CHECK-NEXT: s_and_b64 s[8:9], exec, s[16:17]
141-
; CHECK-NEXT: global_store_dwordx2 v20, v[16:17], s[12:13]
139+
; CHECK-NEXT: v_mov_b32_e32 v17, v16
142140
; CHECK-NEXT: s_cselect_b32 s23, s23, 0
143141
; CHECK-NEXT: s_cselect_b32 s22, s22, 0
144142
; CHECK-NEXT: s_mov_b64 s[8:9], -1
143+
; CHECK-NEXT: global_store_dwordx2 v0, v[16:17], s[12:13]
145144
; CHECK-NEXT: s_branch .LBB0_14
146145
; CHECK-NEXT: .LBB0_13: ; in Loop: Header=BB0_2 Depth=1
147146
; CHECK-NEXT: s_mov_b64 s[8:9], 0
148147
; CHECK-NEXT: v_mov_b64_e32 v[22:23], 0
149-
; CHECK-NEXT: .LBB0_14: ; %Flow6
148+
; CHECK-NEXT: .LBB0_14: ; %Flow8
150149
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
151-
; CHECK-NEXT: v_mov_b64_e32 v[30:31], v[24:25]
150+
; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
151+
; CHECK-NEXT: v_mov_b64_e32 v[16:17], 0
152+
; CHECK-NEXT: v_accvgpr_write_b32 a1, v25
152153
; CHECK-NEXT: .LBB0_15: ; %Flow6
153154
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
154155
; CHECK-NEXT: s_mov_b64 s[24:25], -1
@@ -157,7 +158,7 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
157158
; CHECK-NEXT: ; %bb.16: ; %._crit_edge2105.i.i.i2330
158159
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
159160
; CHECK-NEXT: s_mov_b64 s[24:25], 0
160-
; CHECK-NEXT: global_store_dwordx2 v20, v[20:21], s[12:13]
161+
; CHECK-NEXT: global_store_dwordx2 v0, v[16:17], s[12:13]
161162
; CHECK-NEXT: s_branch .LBB0_1
162163
; CHECK-NEXT: .LBB0_17: ; %DummyReturnBlock
163164
; CHECK-NEXT: s_endpgm

‎llvm/test/CodeGen/AMDGPU/flat-scratch.ll‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4158,8 +4158,7 @@ define void @store_load_i64_aligned(ptr addrspace(5) nocapture %arg) {
41584158
; GFX942-LABEL: store_load_i64_aligned:
41594159
; GFX942: ; %bb.0: ; %bb
41604160
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4161-
; GFX942-NEXT: v_mov_b32_e32 v2, 15
4162-
; GFX942-NEXT: v_mov_b32_e32 v3, 0
4161+
; GFX942-NEXT: v_mov_b64_e32 v[2:3], 15
41634162
; GFX942-NEXT: scratch_store_dwordx2 v0, v[2:3], off sc0 sc1
41644163
; GFX942-NEXT: s_waitcnt vmcnt(0)
41654164
; GFX942-NEXT: scratch_load_dwordx2 v[0:1], v0, off sc0 sc1
@@ -4269,8 +4268,7 @@ define void @store_load_i64_unaligned(ptr addrspace(5) nocapture %arg) {
42694268
; GFX942-LABEL: store_load_i64_unaligned:
42704269
; GFX942: ; %bb.0: ; %bb
42714270
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4272-
; GFX942-NEXT: v_mov_b32_e32 v2, 15
4273-
; GFX942-NEXT: v_mov_b32_e32 v3, 0
4271+
; GFX942-NEXT: v_mov_b64_e32 v[2:3], 15
42744272
; GFX942-NEXT: scratch_store_dwordx2 v0, v[2:3], off sc0 sc1
42754273
; GFX942-NEXT: s_waitcnt vmcnt(0)
42764274
; GFX942-NEXT: scratch_load_dwordx2 v[0:1], v0, off sc0 sc1

‎llvm/test/CodeGen/AMDGPU/imm.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2163,10 +2163,9 @@ define amdgpu_kernel void @store_inline_imm_0.0_f64(ptr addrspace(1) %out) {
21632163
; GFX942-LABEL: store_inline_imm_0.0_f64:
21642164
; GFX942: ; %bb.0:
21652165
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
2166-
; GFX942-NEXT: v_mov_b32_e32 v0, 0
21672166
; GFX942-NEXT: s_mov_b32 s3, 0xf000
21682167
; GFX942-NEXT: s_mov_b32 s2, -1
2169-
; GFX942-NEXT: v_mov_b32_e32 v1, v0
2168+
; GFX942-NEXT: v_mov_b64_e32 v[0:1], 0
21702169
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
21712170
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
21722171
; GFX942-NEXT: s_endpgm

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