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Update TargetLowering.cpp
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llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 9 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -9901,36 +9901,28 @@ SDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const {
99019901
case MVT::i32:
99029902
// This is meant for ARM speficially, which has ROTR but no ROTL.
99039903
if (isOperationLegalOrCustom(ISD::ROTR, VT)) {
9904-
EVT OpVT = Op.getValueType();
9905-
SDValue Src = Op;
9906-
99079904
// ror rtmp, r0, #16
9908-
SDValue Ror16 = DAG.getNode(ISD::ROTR, dl, OpVT, Src,
9909-
DAG.getConstant(16, dl, SHVT));
9905+
SDValue Ror16 =
9906+
DAG.getNode(ISD::ROTR, dl, VT, Op, DAG.getConstant(16, dl, SHVT));
99109907
// eor r1, r0, rtmp ; r1 = r0 ^ (r0 ror 16)
9911-
SDValue Xor1 = DAG.getNode(ISD::XOR, dl, OpVT, Src, Ror16);
9908+
SDValue Xor1 = DAG.getNode(ISD::XOR, dl, VT, Op, Ror16);
99129909

99139910
// bic r1, r1, #0xff0000 (clear bits 16-23)
99149911
// BIC r1, r1, #0xff0000 becomes AND r1, r1, ~0x00ff0000
99159912
// So we need the negated value: ~0x00FF0000 = 0xFF00FFFF
9916-
SDValue Mask = DAG.getConstant(0xFF00FFFFu, dl, OpVT);
9917-
SDValue BicResult = DAG.getNode(ISD::AND, dl, OpVT, Xor1, Mask);
9913+
SDValue Mask = DAG.getConstant(0xFF00FFFFu, dl, VT);
9914+
SDValue BicResult = DAG.getNode(ISD::AND, dl, VT, Xor1, Mask);
99189915

99199916
// mov r1, r1, lsr #8
9920-
SDValue Lsr8 = DAG.getNode(ISD::SRL, dl, OpVT, BicResult,
9917+
SDValue Lsr8 = DAG.getNode(ISD::SRL, dl, VT, BicResult,
99219918
DAG.getConstant(8, dl, SHVT));
99229919

99239920
// ror r0, r0, #8
9924-
SDValue Ror8 = DAG.getNode(ISD::ROTR, dl, OpVT, Src,
9925-
DAG.getConstant(8, dl, SHVT));
9921+
SDValue Ror8 =
9922+
DAG.getNode(ISD::ROTR, dl, VT, Src, DAG.getConstant(8, dl, SHVT));
99269923

99279924
// eor r0, Lsr8, Ror8
9928-
SDValue Result = DAG.getNode(ISD::XOR, dl, OpVT, Lsr8, Ror8);
9929-
9930-
if (OpVT != VT)
9931-
Result = DAG.getNode(ISD::TRUNCATE, dl, VT, Result);
9932-
9933-
return Result;
9925+
return DAG.getNode(ISD::XOR, dl, VT, Lsr8, Ror8);
99349926
}
99359927
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
99369928
Tmp3 = DAG.getNode(ISD::AND, dl, VT, Op,

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