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Pre-commit for widen shuffle mask
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‎llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define <32 x i8> @widen_shuffle_mask_v32i8_to_v16i16(<32 x i8> %a, <32 x i8> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v32i8_to_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
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; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI0_0)
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; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
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; CHECK-NEXT: ret
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%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 32, i32 33, i32 34, i32 35, i32 24, i32 25, i32 26, i32 27, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 30, i32 31>
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ret <32 x i8> %r
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}
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define <32 x i8> @widen_shuffle_mask_v32i8_to_v8i32(<32 x i8> %a, <32 x i8> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v32i8_to_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
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; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI1_0)
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; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
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; CHECK-NEXT: ret
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%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 32, i32 33, i32 34, i32 35, i32 24, i32 25, i32 26, i32 27, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 62, i32 63>
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ret <32 x i8> %r
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}
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define <32 x i8> @widen_shuffle_mask_v32i8_to_v4i64(<32 x i8> %a, <32 x i8> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v32i8_to_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
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; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI2_0)
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; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
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; CHECK-NEXT: ret
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%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
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ret <32 x i8> %r
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}
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define <16 x i16> @widen_shuffle_mask_v16i16_to_v8i32(<16 x i16> %a, <16 x i16> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v16i16_to_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
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; CHECK-NEXT: xvori.b $xr0, $xr2, 0
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; CHECK-NEXT: ret
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%r = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 6, i32 7, i32 16, i32 17, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 24, i32 25, i32 26, i32 27>
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ret <16 x i16> %r
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}
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define <16 x i16> @widen_shuffle_mask_v16i16_to_v4i64(<16 x i16> %a, <16 x i16> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v16i16_to_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
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; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI4_0)
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; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
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; CHECK-NEXT: xvori.b $xr0, $xr2, 0
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; CHECK-NEXT: ret
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%r = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
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ret <16 x i16> %r
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}
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define <8 x i32> @widen_shuffle_mask_v8i32_to_v4i64(<8 x i32> %a, <8 x i32> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v8i32_to_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
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; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI5_0)
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; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
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; CHECK-NEXT: xvori.b $xr0, $xr2, 0
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; CHECK-NEXT: ret
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%r = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 14, i32 15, i32 6, i32 7>
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ret <8 x i32> %r
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}

‎llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll‎

Lines changed: 71 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define <16 x i8> @widen_shuffle_mask_v16i8_to_v8i16(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v16i8_to_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
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; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI0_0)
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; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
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; CHECK-NEXT: ret
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%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 2, i32 3>
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ret <16 x i8> %r
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}
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define <16 x i8> @widen_shuffle_mask_v16i8_to_v4i32(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v16i8_to_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
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; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI1_0)
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; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
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; CHECK-NEXT: ret
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%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
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ret <16 x i8> %r
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}
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define <16 x i8> @widen_shuffle_mask_v16i8_to_v2i64(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v16i8_to_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
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; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI2_0)
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; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
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; CHECK-NEXT: ret
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%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
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ret <16 x i8> %r
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}
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define <8 x i16> @widen_shuffle_mask_v8i16_to_v4i32(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v8i16_to_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr2, 0
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; CHECK-NEXT: ret
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%r = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 12, i32 13, i32 14, i32 15, i32 2, i32 3>
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ret <8 x i16> %r
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}
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define <8 x i16> @widen_shuffle_mask_v8i16_to_v2i64(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v8i16_to_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
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; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI4_0)
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; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr2, 0
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; CHECK-NEXT: ret
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%r = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i16> %r
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}
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define <4 x i32> @widen_shuffle_mask_v4i32_to_v2i64(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: widen_shuffle_mask_v4i32_to_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
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; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI5_0)
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; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr2, 0
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; CHECK-NEXT: ret
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%r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x i32> %r
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}

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