@@ -63,23 +63,23 @@ export void foo() {
6363
6464// Buf2 initialization part 2 - body of RWBuffer<float> C1 constructor with implicit binding that calls the C2 constructor
6565// CHECK: define linkonce_odr void @_ZN4hlsl8RWBufferIdEC1Ejijj(ptr noundef nonnull align 4 dereferenceable(4) %this,
66- // CHECK-SAME: i32 noundef %spaceNo, i32 noundef %range, i32 noundef %index, i32 noundef %order_id )
66+ // CHECK-SAME: i32 noundef %spaceNo, i32 noundef %range, i32 noundef %index, i32 noundef %orderId )
6767// CHECK-NEXT: entry:
6868// CHECK-NEXT: %this.addr = alloca ptr, align 4
6969// CHECK-NEXT: %spaceNo.addr = alloca i32, align 4
7070// CHECK-NEXT: %range.addr = alloca i32, align 4
7171// CHECK-NEXT: %index.addr = alloca i32, align 4
72- // CHECK-NEXT: %order_id .addr = alloca i32, align 4
72+ // CHECK-NEXT: %orderId .addr = alloca i32, align 4
7373// CHECK-NEXT: store ptr %this, ptr %this.addr, align 4
7474// CHECK-NEXT: store i32 %spaceNo, ptr %spaceNo.addr, align 4
7575// CHECK-NEXT: store i32 %range, ptr %range.addr, align 4
7676// CHECK-NEXT: store i32 %index, ptr %index.addr, align 4
77- // CHECK-NEXT: store i32 %order_id , ptr %order_id .addr, align 4
77+ // CHECK-NEXT: store i32 %orderId , ptr %orderId .addr, align 4
7878// CHECK-NEXT: %this1 = load ptr, ptr %this.addr, align 4
7979// CHECK-NEXT: %0 = load i32, ptr %spaceNo.addr, align 4
8080// CHECK-NEXT: %1 = load i32, ptr %range.addr, align 4
8181// CHECK-NEXT: %2 = load i32, ptr %index.addr, align 4
82- // CHECK-NEXT: %3 = load i32, ptr %order_id .addr, align 4
82+ // CHECK-NEXT: %3 = load i32, ptr %orderId .addr, align 4
8383// CHECK-NEXT: call void @_ZN4hlsl8RWBufferIdEC2Ejijj(ptr noundef nonnull align 4 dereferenceable(4) %this1, i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #4
8484// CHECK-NEXT: ret void
8585
@@ -127,23 +127,23 @@ export void foo() {
127127// Buf2 initialization part 3 - body of RWBuffer<float> C2 constructor with implicit binding that initializes
128128// handle with @llvm.dx.resource.handlefromimplicitbinding
129129// CHECK: define linkonce_odr void @_ZN4hlsl8RWBufferIdEC2Ejijj(ptr noundef nonnull align 4 dereferenceable(4) %this,
130- // CHECK-SAME: i32 noundef %spaceNo, i32 noundef %range, i32 noundef %index, i32 noundef %order_id ) unnamed_addr #1 align 2 {
130+ // CHECK-SAME: i32 noundef %spaceNo, i32 noundef %range, i32 noundef %index, i32 noundef %orderId ) unnamed_addr #1 align 2 {
131131// CHECK-NEXT: entry:
132132// CHECK-NEXT: %this.addr = alloca ptr, align 4
133133// CHECK-NEXT: %spaceNo.addr = alloca i32, align 4
134134// CHECK-NEXT: %range.addr = alloca i32, align 4
135135// CHECK-NEXT: %index.addr = alloca i32, align 4
136- // CHECK-NEXT: %order_id .addr = alloca i32, align 4
136+ // CHECK-NEXT: %orderId .addr = alloca i32, align 4
137137// CHECK-NEXT: store ptr %this, ptr %this.addr, align 4
138138// CHECK-NEXT: store i32 %spaceNo, ptr %spaceNo.addr, align 4
139139// CHECK-NEXT: store i32 %range, ptr %range.addr, align 4
140140// CHECK-NEXT: store i32 %index, ptr %index.addr, align 4
141- // CHECK-NEXT: store i32 %order_id , ptr %order_id .addr, align 4
141+ // CHECK-NEXT: store i32 %orderId , ptr %orderId .addr, align 4
142142// CHECK-NEXT: %this1 = load ptr, ptr %this.addr, align 4
143143// CHECK-NEXT: %0 = load i32, ptr %spaceNo.addr, align 4
144144// CHECK-NEXT: %1 = load i32, ptr %range.addr, align 4
145145// CHECK-NEXT: %2 = load i32, ptr %index.addr, align 4
146- // CHECK-NEXT: %3 = load i32, ptr %order_id .addr, align 4
146+ // CHECK-NEXT: %3 = load i32, ptr %orderId .addr, align 4
147147// CHECK-NEXT: %4 = call target("dx.TypedBuffer", double, 1, 0, 0) @llvm.dx.resource.handlefromimplicitbinding.tdx.TypedBuffer_f64_1_0_0t(i32 %3, i32 %0, i32 %1, i32 %2, i1 false)
148148// CHECK-NEXT: %__handle = getelementptr inbounds nuw %"class.hlsl::RWBuffer.0", ptr %this1, i32 0, i32 0
149149// CHECK-NEXT: store target("dx.TypedBuffer", double, 1, 0, 0) %4, ptr %__handle, align 4
0 commit comments