[ARM] Optimise loads of fp16 arguments from i32 stack slots

Author: ostannard

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -15275,10 +15275,19 @@ static SDValue PerformVMOVhrCombine(SDNode *N,
   // fold (VMOVhr (load x)) -> (load (f16*)x)
   if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(Op0)) {
     if (LN0->hasOneUse() && LN0->isUnindexed() &&
-        LN0->getMemoryVT() == MVT::i16) {
-      SDValue Load =
-          DCI.DAG.getLoad(N->getValueType(0), SDLoc(N), LN0->getChain(),
-                          LN0->getBasePtr(), LN0->getMemOperand());
+        (LN0->getMemoryVT() == MVT::i16 || LN0->getMemoryVT() == MVT::i32)) {
+      SDValue Addr = LN0->getBasePtr();
+      unsigned PtrOffset = 0;
+      if (DCI.DAG.getDataLayout().isBigEndian() &&
+          LN0->getMemoryVT() == MVT::i32) {
+        PtrOffset = 2;
+        Addr = DCI.DAG.getObjectPtrOffset(SDLoc(N), Addr,
+                                          TypeSize::getFixed(PtrOffset));
+      }
+      SDValue Load = DCI.DAG.getLoad(
+          N->getValueType(0), SDLoc(N), LN0->getChain(), Addr,
+          LN0->getPointerInfo().getWithOffset(PtrOffset), LN0->getAlign(),
+          LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
       DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Load.getValue(0));
       DCI.DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Load.getValue(1));
       return Load;

llvm/test/CodeGen/Thumb2/fp16-pcs.ll

@@ -78,15 +78,13 @@ define arm_aapcscc half @callee_soft_half_on_stack(float %r0, float %r1, float %
 ;
 ; LE-FP16-LABEL: callee_soft_half_on_stack:
 ; LE-FP16:       @ %bb.0: @ %entry
-; LE-FP16-NEXT:    ldr r0, [sp]
-; LE-FP16-NEXT:    vmov.f16 s0, r0
+; LE-FP16-NEXT:    vldr.16 s0, [sp]
 ; LE-FP16-NEXT:    vmov r0, s0
 ; LE-FP16-NEXT:    bx lr
 ;
 ; BE-FP16-LABEL: callee_soft_half_on_stack:
 ; BE-FP16:       @ %bb.0: @ %entry
-; BE-FP16-NEXT:    ldr r0, [sp]
-; BE-FP16-NEXT:    vmov.f16 s0, r0
+; BE-FP16-NEXT:    vldr.16 s0, [sp, #2]
 ; BE-FP16-NEXT:    vmov r0, s0
 ; BE-FP16-NEXT:    bx lr
 entry:
@@ -224,14 +222,12 @@ define arm_aapcs_vfpcc half @callee_hard_half_on_stack(float %s0, float %s1, flo
 ;
 ; LE-FP16-LABEL: callee_hard_half_on_stack:
 ; LE-FP16:       @ %bb.0: @ %entry
-; LE-FP16-NEXT:    ldr r0, [sp]
-; LE-FP16-NEXT:    vmov.f16 s0, r0
+; LE-FP16-NEXT:    vldr.16 s0, [sp]
 ; LE-FP16-NEXT:    bx lr
 ;
 ; BE-FP16-LABEL: callee_hard_half_on_stack:
 ; BE-FP16:       @ %bb.0: @ %entry
-; BE-FP16-NEXT:    ldr r0, [sp]
-; BE-FP16-NEXT:    vmov.f16 s0, r0
+; BE-FP16-NEXT:    vldr.16 s0, [sp, #2]
 ; BE-FP16-NEXT:    bx lr
 entry:
   ret half %f