Skip to content

Commit 30b3e70

Browse files
topperctopperc
committed
[RISCV] Remove experimental from Smctr and Ssctr.
1 parent 6beb6f3 commit 30b3e70

File tree

7 files changed

+29
-28
lines changed

7 files changed

+29
-28
lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,7 @@
128128
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
129129
// CHECK-NEXT: smcntrpmf 1.0 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)
130130
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
131+
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
131132
// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
132133
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
133134
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
@@ -140,6 +141,7 @@
140141
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
141142
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
142143
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
144+
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
143145
// CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap Supervisor Level)
144146
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
145147
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
@@ -214,8 +216,6 @@
214216
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
215217
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
216218
// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product)
217-
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
218-
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
219219
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
220220
// CHECK-NEXT: xqccmp 0.3 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
221221
// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC Arithmetic Extension)

‎llvm/docs/ReleaseNotes.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ Changes to the RISC-V Backend
118118
* `llvm-objdump` now has basic support for switching between disassembling code
119119
and data using mapping symbols such as `$x` and `$d`. Switching architectures
120120
using `$x` with an architecture string suffix is not yet supported.
121+
* Ssctr and Smctr extensions are no longer experimental.
121122

122123
Changes to the WebAssembly Backend
123124
----------------------------------

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1055,13 +1055,13 @@ def FeatureStdExtSupm
10551055
"Indicates User-mode Pointer Masking">;
10561056

10571057
def FeatureStdExtSmctr
1058-
: RISCVExperimentalExtension<1, 0,
1059-
"Control Transfer Records Machine Level",
1060-
[FeatureStdExtSscsrind]>;
1058+
: RISCVExtension<1, 0,
1059+
"Control Transfer Records Machine Level",
1060+
[FeatureStdExtSscsrind]>;
10611061
def FeatureStdExtSsctr
1062-
: RISCVExperimentalExtension<1, 0,
1063-
"Control Transfer Records Supervisor Level",
1064-
[FeatureStdExtSscsrind]>;
1062+
: RISCVExtension<1, 0,
1063+
"Control Transfer Records Supervisor Level",
1064+
[FeatureStdExtSscsrind]>;
10651065
def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
10661066
AssemblerPredicate<(any_of FeatureStdExtSmctr, FeatureStdExtSsctr),
10671067
"'Smctr' (Control Transfer Records Machine Level) or "

‎llvm/test/CodeGen/RISCV/attributes.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -173,8 +173,8 @@
173173
; RUN: llc -mtriple=riscv32 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
174174
; RUN: llc -mtriple=riscv32 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
175175
; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
176-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
177-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s
176+
; RUN: llc -mtriple=riscv32 -mattr=+smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
177+
; RUN: llc -mtriple=riscv32 -mattr=+ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s
178178

179179
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
180180
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -336,8 +336,8 @@
336336
; RUN: llc -mtriple=riscv64 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
337337
; RUN: llc -mtriple=riscv64 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
338338
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
339-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
340-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
339+
; RUN: llc -mtriple=riscv64 -mattr=+smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
340+
; RUN: llc -mtriple=riscv64 -mattr=+ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
341341
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
342342
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
343343
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s

‎llvm/test/CodeGen/RISCV/features-info.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,6 @@
2727
; CHECK-NEXT: experimental - Experimental intrinsics.
2828
; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)).
2929
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
30-
; CHECK-NEXT: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level).
31-
; CHECK-NEXT: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
3230
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
3331
; CHECK-NEXT: experimental-xqccmp - 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves).
3432
; CHECK-NEXT: experimental-xqcia - 'Xqcia' (Qualcomm uC Arithmetic Extension).
@@ -145,6 +143,7 @@
145143
; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level).
146144
; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering).
147145
; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level).
146+
; CHECK-NEXT: smctr - 'Smctr' (Control Transfer Records Machine Level).
148147
; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap Machine Level).
149148
; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection).
150149
; CHECK-NEXT: smmpm - 'Smmpm' (Machine-level Pointer Masking for M-mode).
@@ -157,6 +156,7 @@
157156
; CHECK-NEXT: sscofpmf - 'Sscofpmf' (Count Overflow and Mode-Based Filtering).
158157
; CHECK-NEXT: sscounterenw - 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero).
159158
; CHECK-NEXT: sscsrind - 'Sscsrind' (Indirect CSR Access Supervisor Level).
159+
; CHECK-NEXT: ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
160160
; CHECK-NEXT: ssdbltrp - 'Ssdbltrp' (Double Trap Supervisor Level).
161161
; CHECK-NEXT: ssnpm - 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode).
162162
; CHECK-NEXT: sspm - 'Sspm' (Indicates Supervisor-mode Pointer Masking).

‎llvm/test/MC/RISCV/smctr-ssctr-valid.s‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,22 @@
1-
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-smctr -M no-aliases -show-encoding \
1+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+smctr -M no-aliases -show-encoding \
22
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
3-
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-smctr -M no-aliases -show-encoding \
3+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+smctr -M no-aliases -show-encoding \
44
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
5-
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ssctr -M no-aliases -show-encoding \
5+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+ssctr -M no-aliases -show-encoding \
66
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
7-
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ssctr -M no-aliases -show-encoding \
7+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+ssctr -M no-aliases -show-encoding \
88
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
9-
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-smctr < %s \
10-
# RUN: | llvm-objdump --mattr=+experimental-smctr -M no-aliases -d - \
9+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+smctr < %s \
10+
# RUN: | llvm-objdump --mattr=+smctr -M no-aliases -d - \
1111
# RUN: | FileCheck -check-prefix=CHECK-INST %s
12-
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-smctr < %s \
13-
# RUN: | llvm-objdump --mattr=+experimental-smctr -M no-aliases -d - \
12+
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+smctr < %s \
13+
# RUN: | llvm-objdump --mattr=+smctr -M no-aliases -d - \
1414
# RUN: | FileCheck -check-prefix=CHECK-INST %s
15-
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-ssctr < %s \
16-
# RUN: | llvm-objdump --mattr=+experimental-ssctr -M no-aliases -d - \
15+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+ssctr < %s \
16+
# RUN: | llvm-objdump --mattr=+ssctr -M no-aliases -d - \
1717
# RUN: | FileCheck -check-prefix=CHECK-INST %s
18-
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-ssctr < %s \
19-
# RUN: | llvm-objdump --mattr=+experimental-ssctr -M no-aliases -d - \
18+
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+ssctr < %s \
19+
# RUN: | llvm-objdump --mattr=+ssctr -M no-aliases -d - \
2020
# RUN: | FileCheck -check-prefix=CHECK-INST %s
2121

2222
# RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1099,6 +1099,7 @@ R"(All available -march extensions for RISC-V
10991099
smcdeleg 1.0
11001100
smcntrpmf 1.0
11011101
smcsrind 1.0
1102+
smctr 1.0
11021103
smdbltrp 1.0
11031104
smepmp 1.0
11041105
smmpm 1.0
@@ -1111,6 +1112,7 @@ R"(All available -march extensions for RISC-V
11111112
sscofpmf 1.0
11121113
sscounterenw 1.0
11131114
sscsrind 1.0
1115+
ssctr 1.0
11141116
ssdbltrp 1.0
11151117
ssnpm 1.0
11161118
sspm 1.0
@@ -1185,8 +1187,6 @@ Experimental extensions
11851187
zvbc32e 0.7
11861188
zvkgs 0.7
11871189
zvqdotq 0.0
1188-
smctr 1.0
1189-
ssctr 1.0
11901190
svukte 0.3
11911191
xqccmp 0.3
11921192
xqcia 0.7

0 commit comments

Comments
 (0)