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[RISCV] Factor out the core part of LMULWriteResMXVariant. NFC (#162347)
LMULWriteResMXVariant is a helper class that makes creating LMUL-aware `SchedVar` easier. In preparation for later patches that require - LMUL- _and_ SEW-aware `SchedVar` - Assign different processor resources for predicated and non-predicated variants I factor out the core logics of LMULWriteResMXVariant into another impl class, such that it'll be easier to add _"LMULSEWWriteResMXSEWVariant"_ easier later. I also extend this class so that users can customize processor resources for the non-predicated variant. Despite these, this patch is still a NFC. I thought it'll be cleaner not to mix the changes here into later patches.
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‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -567,9 +567,12 @@ multiclass SiFive7WriteResBase<int VLEN,
567567
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
568568
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c;
569569
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
570-
defm : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, [VCQ, VL],
571-
4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
572-
[0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
570+
defm : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred,
571+
// Predicated
572+
[VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)],
573+
// Not Predicated
574+
[VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)],
575+
mx, IsWorstCase>;
573576
let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
574577
defm : LMULWriteResMX<"WriteVLDUX8", [VCQ, VL], mx, IsWorstCase>;
575578
defm : LMULWriteResMX<"WriteVLDOX8", [VCQ, VL], mx, IsWorstCase>;
@@ -587,9 +590,12 @@ multiclass SiFive7WriteResBase<int VLEN,
587590
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
588591
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16, VLEN>.c;
589592
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
590-
defm : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred, [VCQ, VL],
591-
4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
592-
[0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
593+
defm : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred,
594+
// Predicated
595+
[VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)],
596+
// Not Predicated
597+
[VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)],
598+
mx, IsWorstCase>;
593599
let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
594600
defm : LMULWriteResMX<"WriteVLDUX16", [VCQ, VL], mx, IsWorstCase>;
595601
defm : LMULWriteResMX<"WriteVLDOX16", [VCQ, VL], mx, IsWorstCase>;
@@ -604,9 +610,12 @@ multiclass SiFive7WriteResBase<int VLEN,
604610
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
605611
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32, VLEN>.c;
606612
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
607-
defm : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred, [VCQ, VL],
608-
4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
609-
[0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
613+
defm : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred,
614+
// Predicated
615+
[VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)],
616+
// Not Predicated
617+
[VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)],
618+
mx, IsWorstCase>;
610619
let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
611620
defm : LMULWriteResMX<"WriteVLDUX32", [VCQ, VL], mx, IsWorstCase>;
612621
defm : LMULWriteResMX<"WriteVLDOX32", [VCQ, VL], mx, IsWorstCase>;
@@ -621,9 +630,12 @@ multiclass SiFive7WriteResBase<int VLEN,
621630
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
622631
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64, VLEN>.c;
623632
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
624-
defm : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred, [VCQ, VL],
625-
4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
626-
[0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
633+
defm : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred,
634+
// Predicated
635+
[VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)],
636+
// Not Predicated
637+
[VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)],
638+
mx, IsWorstCase>;
627639
let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
628640
defm : LMULWriteResMX<"WriteVLDUX64", [VCQ, VL], mx, IsWorstCase>;
629641
defm : LMULWriteResMX<"WriteVLDOX64", [VCQ, VL], mx, IsWorstCase>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td‎

Lines changed: 35 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -67,42 +67,41 @@ multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,
6767
// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has
6868
// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite
6969
// is created similarly if IsWorstCase is true.
70-
multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
71-
list<ProcResourceKind> resources,
72-
int predLat, list<int> predAcquireCycles,
73-
list<int> predReleaseCycles, int noPredLat,
74-
list<int> noPredAcquireCycles,
75-
list<int> noPredReleaseCycles,
76-
string mx, bit IsWorstCase> {
77-
defvar nameMX = name # "_" # mx;
78-
70+
multiclass LMULWriteResVariantImpl<string name, string writeResName, SchedPredicateBase Pred,
71+
list<ProcResourceKind> predResources,
72+
int predLat, list<int> predAcquireCycles,
73+
list<int> predReleaseCycles,
74+
list<ProcResourceKind> noPredResources,
75+
int noPredLat, list<int> noPredAcquireCycles,
76+
list<int> noPredReleaseCycles,
77+
bit IsWorstCase> {
7978
// Define the different behaviors
80-
def nameMX # "_Pred" : SchedWriteRes<resources>{
79+
def writeResName # "_Pred" : SchedWriteRes<predResources>{
8180
let Latency = predLat;
8281
let AcquireAtCycles = predAcquireCycles;
8382
let ReleaseAtCycles = predReleaseCycles;
8483
}
85-
def nameMX # "_NoPred" : SchedWriteRes<resources> {
84+
def writeResName # "_NoPred" : SchedWriteRes<noPredResources> {
8685
let Latency = noPredLat;
8786
let AcquireAtCycles = noPredAcquireCycles;
8887
let ReleaseAtCycles = noPredReleaseCycles;
8988
}
9089

9190
// Define SchedVars
92-
def nameMX # PredSchedVar
93-
: SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>;
94-
def nameMX # NoPredSchedVar
95-
: SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX #"_NoPred")]>;
91+
def writeResName # PredSchedVar
92+
: SchedVar<Pred, [!cast<SchedWriteRes>(NAME # writeResName # "_Pred")]>;
93+
def writeResName # NoPredSchedVar
94+
: SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # writeResName #"_NoPred")]>;
9695
// Allow multiclass to refer to SchedVars -- need to have NAME prefix.
97-
defvar PredSchedVar = !cast<SchedVar>(NAME # nameMX # PredSchedVar);
98-
defvar NoPredSchedVar = !cast<SchedVar>(NAME # nameMX # NoPredSchedVar);
96+
defvar PredSchedVar = !cast<SchedVar>(NAME # writeResName # PredSchedVar);
97+
defvar NoPredSchedVar = !cast<SchedVar>(NAME # writeResName # NoPredSchedVar);
9998

10099
// Tie behavior to predicate
101-
def NAME # nameMX # "_Variant"
100+
def NAME # writeResName # "_Variant"
102101
: SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>;
103102
def : SchedAlias<
104-
!cast<SchedReadWrite>(nameMX),
105-
!cast<SchedReadWrite>(NAME # nameMX # "_Variant")>;
103+
!cast<SchedReadWrite>(writeResName),
104+
!cast<SchedReadWrite>(NAME # writeResName # "_Variant")>;
106105

107106
if IsWorstCase then {
108107
def NAME # name # "_WorstCase_Variant"
@@ -113,6 +112,22 @@ multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
113112
}
114113
}
115114

115+
multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
116+
list<ProcResourceKind> predResources,
117+
int predLat, list<int> predAcquireCycles,
118+
list<int> predReleaseCycles,
119+
list<ProcResourceKind> noPredResources,
120+
int noPredLat, list<int> noPredAcquireCycles,
121+
list<int> noPredReleaseCycles,
122+
string mx, bit IsWorstCase> {
123+
defm "" : LMULWriteResVariantImpl<name, name # "_" # mx, Pred, predResources,
124+
predLat, predAcquireCycles,
125+
predReleaseCycles, noPredResources,
126+
noPredLat, noPredAcquireCycles,
127+
noPredReleaseCycles,
128+
IsWorstCase>;
129+
}
130+
116131
// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and
117132
// ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
118133
// SchedMxList variants above. Each multiclass is responsible for defining

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