[RISCV] Recognize de-interleave shuffles with 2 sources.

topperc · topperc · commit 30fd9e3dd4ec · 2025-02-14T15:19:11.000-08:00
We can use vnsrl+trunc on each source and concatenate the results
with vslideup.

For low LMUL it would be better to concat first, but I'm leaving
this for later.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5579,6 +5579,20 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
           1 < count_if(Mask, [](int Idx) { return Idx != -1; })) {
         if (SDValue Src = getSingleShuffleSrc(VT, ContainerVT, V1, V2))
           return getDeinterleaveShiftAndTrunc(DL, VT, Src, Factor, Index, DAG);
+        if (1 < count_if(Mask,
+                         [&Mask](int Idx) { return Idx < (int)Mask.size(); }) &&
+            1 < count_if(Mask, [&Mask](int Idx) {
+              return Idx >= (int)Mask.size();
+            })) {
+          // Narrow each source and concatenate them.
+          // FIXME: For small LMUL it is better to concatenate first.
+          MVT HalfVT = VT.getHalfNumVectorElementsVT();
+          SDValue Lo =
+              getDeinterleaveShiftAndTrunc(DL, HalfVT, V1, Factor, Index, DAG);
+          SDValue Hi =
+              getDeinterleaveShiftAndTrunc(DL, HalfVT, V2, Factor, Index, DAG);
+          return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
+        }
       }
     }
   }
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
@@ -10,34 +10,26 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
 ; CHECK-LABEL: vector_deinterleave_load_v16i1_v32i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT:    vmv.v.i v10, 0
-; CHECK-NEXT:    vid.v v9
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vlm.v v8, (a0)
-; CHECK-NEXT:    li a0, -256
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT:    vadd.vv v11, v9, v9
-; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vmv.s.x v9, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vadd.vi v12, v11, -16
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v9, v8, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT:    vslidedown.vi v0, v8, 2
+; CHECK-NEXT:    vslidedown.vi v0, v0, 2
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vnsrl.wi v10, v9, 0
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT:    vadd.vi v11, v11, -15
-; CHECK-NEXT:    vmerge.vim v13, v10, 1, v0
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vnsrl.wi v10, v8, 0
+; CHECK-NEXT:    vnsrl.wi v9, v9, 8
+; CHECK-NEXT:    vnsrl.wi v11, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v8, v8, 8
-; CHECK-NEXT:    vmv1r.v v0, v9
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT:    vrgather.vv v10, v13, v12, v0.t
-; CHECK-NEXT:    vrgather.vv v8, v13, v11, v0.t
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vslideup.vi v10, v11, 8
+; CHECK-NEXT:    vslideup.vi v9, v8, 8
 ; CHECK-NEXT:    vmsne.vi v0, v10, 0
-; CHECK-NEXT:    vmsne.vi v8, v8, 0
+; CHECK-NEXT:    vmsne.vi v8, v9, 0
 ; CHECK-NEXT:    ret
   %vec = load <32 x i1>, ptr %p
   %deinterleaved.results = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
@@ -374,19 +374,17 @@ define void @deinterleave4_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
 ; CHECK-LABEL: deinterleave4_0_i8_two_source:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vle8.v v9, (a1)
-; CHECK-NEXT:    vmv.v.i v0, 12
-; CHECK-NEXT:    vid.v v10
-; CHECK-NEXT:    vsll.vi v10, v10, 2
-; CHECK-NEXT:    vadd.vi v10, v10, -8
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vle8.v v9, (a0)
 ; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v8, v8, 0
+; CHECK-NEXT:    vnsrl.wi v9, v9, 0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v8, v8, 0
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; CHECK-NEXT:    vse8.v v8, (a2)
+; CHECK-NEXT:    vnsrl.wi v9, v9, 0
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslideup.vi v9, v8, 4
+; CHECK-NEXT:    vse8.v v9, (a2)
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <8 x i8>, ptr %in0, align 1
@@ -402,20 +400,15 @@ define void @deinterleave4_8_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a1)
 ; CHECK-NEXT:    vle8.v v9, (a0)
-; CHECK-NEXT:    li a0, -1
-; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT:    vslidedown.vi v10, v8, 4
-; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT:    vwaddu.vv v11, v8, v10
-; CHECK-NEXT:    vwmaccu.vx v11, a0, v10
-; CHECK-NEXT:    vmv.v.i v0, 12
 ; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v9, 8
+; CHECK-NEXT:    vnsrl.wi v8, v8, 8
+; CHECK-NEXT:    vnsrl.wi v9, v9, 8
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v8, v8, 0
+; CHECK-NEXT:    vnsrl.wi v9, v9, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vmerge.vvm v8, v8, v11, v0
-; CHECK-NEXT:    vse8.v v8, (a2)
+; CHECK-NEXT:    vslideup.vi v9, v8, 4
+; CHECK-NEXT:    vse8.v v9, (a2)
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <8 x i8>, ptr %in0, align 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
@@ -556,33 +556,27 @@ define void @vnsrl_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
 ; V-LABEL: vnsrl_0_i8_two_source:
 ; V:       # %bb.0: # %entry
 ; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
-; V-NEXT:    vle8.v v8, (a0)
-; V-NEXT:    vle8.v v9, (a1)
-; V-NEXT:    vmv.v.i v0, -16
-; V-NEXT:    vid.v v10
-; V-NEXT:    vadd.vv v10, v10, v10
-; V-NEXT:    vadd.vi v10, v10, -8
+; V-NEXT:    vle8.v v8, (a1)
+; V-NEXT:    vle8.v v9, (a0)
 ; V-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma
 ; V-NEXT:    vnsrl.wi v8, v8, 0
-; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, mu
-; V-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; V-NEXT:    vse8.v v8, (a2)
+; V-NEXT:    vnsrl.wi v9, v9, 0
+; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; V-NEXT:    vslideup.vi v9, v8, 4
+; V-NEXT:    vse8.v v9, (a2)
 ; V-NEXT:    ret
 ;
 ; ZVE32F-LABEL: vnsrl_0_i8_two_source:
 ; ZVE32F:       # %bb.0: # %entry
 ; ZVE32F-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
-; ZVE32F-NEXT:    vle8.v v8, (a0)
-; ZVE32F-NEXT:    vle8.v v9, (a1)
-; ZVE32F-NEXT:    vmv.v.i v0, -16
-; ZVE32F-NEXT:    vid.v v10
-; ZVE32F-NEXT:    vadd.vv v10, v10, v10
-; ZVE32F-NEXT:    vadd.vi v10, v10, -8
+; ZVE32F-NEXT:    vle8.v v8, (a1)
+; ZVE32F-NEXT:    vle8.v v9, (a0)
 ; ZVE32F-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; ZVE32F-NEXT:    vnsrl.wi v8, v8, 0
-; ZVE32F-NEXT:    vsetivli zero, 8, e8, mf4, ta, mu
-; ZVE32F-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; ZVE32F-NEXT:    vse8.v v8, (a2)
+; ZVE32F-NEXT:    vnsrl.wi v9, v9, 0
+; ZVE32F-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; ZVE32F-NEXT:    vslideup.vi v9, v8, 4
+; ZVE32F-NEXT:    vse8.v v9, (a2)
 ; ZVE32F-NEXT:    ret
 entry:
   %0 = load <8 x i8>, ptr %in0, align 1
@@ -596,33 +590,27 @@ define void @vnsrl_8_8_two_source(ptr %in0, ptr %in1, ptr %out) {
 ; V-LABEL: vnsrl_8_8_two_source:
 ; V:       # %bb.0: # %entry
 ; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
-; V-NEXT:    vle8.v v8, (a0)
-; V-NEXT:    vle8.v v9, (a1)
-; V-NEXT:    vmv.v.i v0, -16
-; V-NEXT:    vid.v v10
-; V-NEXT:    vadd.vv v10, v10, v10
-; V-NEXT:    vadd.vi v10, v10, -7
+; V-NEXT:    vle8.v v8, (a1)
+; V-NEXT:    vle8.v v9, (a0)
 ; V-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma
 ; V-NEXT:    vnsrl.wi v8, v8, 8
-; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, mu
-; V-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; V-NEXT:    vse8.v v8, (a2)
+; V-NEXT:    vnsrl.wi v9, v9, 8
+; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; V-NEXT:    vslideup.vi v9, v8, 4
+; V-NEXT:    vse8.v v9, (a2)
 ; V-NEXT:    ret
 ;
 ; ZVE32F-LABEL: vnsrl_8_8_two_source:
 ; ZVE32F:       # %bb.0: # %entry
 ; ZVE32F-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
-; ZVE32F-NEXT:    vle8.v v8, (a0)
-; ZVE32F-NEXT:    vle8.v v9, (a1)
-; ZVE32F-NEXT:    vmv.v.i v0, -16
-; ZVE32F-NEXT:    vid.v v10
-; ZVE32F-NEXT:    vadd.vv v10, v10, v10
-; ZVE32F-NEXT:    vadd.vi v10, v10, -7
+; ZVE32F-NEXT:    vle8.v v8, (a1)
+; ZVE32F-NEXT:    vle8.v v9, (a0)
 ; ZVE32F-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; ZVE32F-NEXT:    vnsrl.wi v8, v8, 8
-; ZVE32F-NEXT:    vsetivli zero, 8, e8, mf4, ta, mu
-; ZVE32F-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; ZVE32F-NEXT:    vse8.v v8, (a2)
+; ZVE32F-NEXT:    vnsrl.wi v9, v9, 8
+; ZVE32F-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; ZVE32F-NEXT:    vslideup.vi v9, v8, 4
+; ZVE32F-NEXT:    vse8.v v9, (a2)
 ; ZVE32F-NEXT:    ret
 entry:
   %0 = load <8 x i8>, ptr %in0, align 1
@@ -636,33 +624,27 @@ define void @vnsrl_0_i16_two_source(ptr %in0, ptr %in1, ptr %out) {
 ; V-LABEL: vnsrl_0_i16_two_source:
 ; V:       # %bb.0: # %entry
 ; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
-; V-NEXT:    vle16.v v8, (a0)
-; V-NEXT:    vle16.v v9, (a1)
-; V-NEXT:    vid.v v10
-; V-NEXT:    vadd.vv v10, v10, v10
-; V-NEXT:    vadd.vi v10, v10, -4
-; V-NEXT:    vmv.v.i v0, 12
+; V-NEXT:    vle16.v v8, (a1)
+; V-NEXT:    vle16.v v9, (a0)
 ; V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
 ; V-NEXT:    vnsrl.wi v8, v8, 0
-; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, mu
-; V-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; V-NEXT:    vse16.v v8, (a2)
+; V-NEXT:    vnsrl.wi v9, v9, 0
+; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
+; V-NEXT:    vslideup.vi v9, v8, 2
+; V-NEXT:    vse16.v v9, (a2)
 ; V-NEXT:    ret
 ;
 ; ZVE32F-LABEL: vnsrl_0_i16_two_source:
 ; ZVE32F:       # %bb.0: # %entry
 ; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; ZVE32F-NEXT:    vle16.v v8, (a0)
-; ZVE32F-NEXT:    vle16.v v9, (a1)
-; ZVE32F-NEXT:    vid.v v10
-; ZVE32F-NEXT:    vadd.vv v10, v10, v10
-; ZVE32F-NEXT:    vadd.vi v10, v10, -4
-; ZVE32F-NEXT:    vmv.v.i v0, 12
+; ZVE32F-NEXT:    vle16.v v8, (a1)
+; ZVE32F-NEXT:    vle16.v v9, (a0)
 ; ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma
 ; ZVE32F-NEXT:    vnsrl.wi v8, v8, 0
-; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
-; ZVE32F-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; ZVE32F-NEXT:    vse16.v v8, (a2)
+; ZVE32F-NEXT:    vnsrl.wi v9, v9, 0
+; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; ZVE32F-NEXT:    vslideup.vi v9, v8, 2
+; ZVE32F-NEXT:    vse16.v v9, (a2)
 ; ZVE32F-NEXT:    ret
 entry:
   %0 = load <4 x i16>, ptr %in0, align 2
@@ -678,33 +660,25 @@ define void @vnsrl_16_i16_two_source(ptr %in0, ptr %in1, ptr %out) {
 ; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
 ; V-NEXT:    vle16.v v8, (a1)
 ; V-NEXT:    vle16.v v9, (a0)
-; V-NEXT:    li a0, -1
 ; V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; V-NEXT:    vslidedown.vi v10, v8, 2
-; V-NEXT:    vwaddu.vv v11, v8, v10
-; V-NEXT:    vwmaccu.vx v11, a0, v10
-; V-NEXT:    vmv.v.i v0, 12
-; V-NEXT:    vnsrl.wi v8, v9, 16
+; V-NEXT:    vnsrl.wi v8, v8, 16
+; V-NEXT:    vnsrl.wi v9, v9, 16
 ; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
-; V-NEXT:    vmerge.vvm v8, v8, v11, v0
-; V-NEXT:    vse16.v v8, (a2)
+; V-NEXT:    vslideup.vi v9, v8, 2
+; V-NEXT:    vse16.v v9, (a2)
 ; V-NEXT:    ret
 ;
 ; ZVE32F-LABEL: vnsrl_16_i16_two_source:
 ; ZVE32F:       # %bb.0: # %entry
 ; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
 ; ZVE32F-NEXT:    vle16.v v8, (a1)
 ; ZVE32F-NEXT:    vle16.v v9, (a0)
-; ZVE32F-NEXT:    li a0, -1
 ; ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma
-; ZVE32F-NEXT:    vslidedown.vi v10, v8, 2
-; ZVE32F-NEXT:    vwaddu.vv v11, v8, v10
-; ZVE32F-NEXT:    vwmaccu.vx v11, a0, v10
-; ZVE32F-NEXT:    vmv.v.i v0, 12
-; ZVE32F-NEXT:    vnsrl.wi v8, v9, 16
+; ZVE32F-NEXT:    vnsrl.wi v8, v8, 16
+; ZVE32F-NEXT:    vnsrl.wi v9, v9, 16
 ; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; ZVE32F-NEXT:    vmerge.vvm v8, v8, v11, v0
-; ZVE32F-NEXT:    vse16.v v8, (a2)
+; ZVE32F-NEXT:    vslideup.vi v9, v8, 2
+; ZVE32F-NEXT:    vse16.v v9, (a2)
 ; ZVE32F-NEXT:    ret
 entry:
   %0 = load <4 x i16>, ptr %in0, align 2
@@ -718,33 +692,27 @@ define void @vnsrl_0_half_two_source(ptr %in0, ptr %in1, ptr %out) {
 ; V-LABEL: vnsrl_0_half_two_source:
 ; V:       # %bb.0: # %entry
 ; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
-; V-NEXT:    vle16.v v8, (a0)
-; V-NEXT:    vle16.v v9, (a1)
-; V-NEXT:    vid.v v10
-; V-NEXT:    vadd.vv v10, v10, v10
-; V-NEXT:    vadd.vi v10, v10, -4
-; V-NEXT:    vmv.v.i v0, 12
+; V-NEXT:    vle16.v v8, (a1)
+; V-NEXT:    vle16.v v9, (a0)
 ; V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
 ; V-NEXT:    vnsrl.wi v8, v8, 0
-; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, mu
-; V-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; V-NEXT:    vse16.v v8, (a2)
+; V-NEXT:    vnsrl.wi v9, v9, 0
+; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
+; V-NEXT:    vslideup.vi v9, v8, 2
+; V-NEXT:    vse16.v v9, (a2)
 ; V-NEXT:    ret
 ;
 ; ZVE32F-LABEL: vnsrl_0_half_two_source:
 ; ZVE32F:       # %bb.0: # %entry
 ; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; ZVE32F-NEXT:    vle16.v v8, (a0)
-; ZVE32F-NEXT:    vle16.v v9, (a1)
-; ZVE32F-NEXT:    vid.v v10
-; ZVE32F-NEXT:    vadd.vv v10, v10, v10
-; ZVE32F-NEXT:    vadd.vi v10, v10, -4
-; ZVE32F-NEXT:    vmv.v.i v0, 12
+; ZVE32F-NEXT:    vle16.v v8, (a1)
+; ZVE32F-NEXT:    vle16.v v9, (a0)
 ; ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma
 ; ZVE32F-NEXT:    vnsrl.wi v8, v8, 0
-; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
-; ZVE32F-NEXT:    vrgather.vv v8, v9, v10, v0.t
-; ZVE32F-NEXT:    vse16.v v8, (a2)
+; ZVE32F-NEXT:    vnsrl.wi v9, v9, 0
+; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; ZVE32F-NEXT:    vslideup.vi v9, v8, 2
+; ZVE32F-NEXT:    vse16.v v9, (a2)
 ; ZVE32F-NEXT:    ret
 entry:
   %0 = load <4 x half>, ptr %in0, align 2
@@ -760,33 +728,25 @@ define void @vnsrl_16_half_two_source(ptr %in0, ptr %in1, ptr %out) {
 ; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
 ; V-NEXT:    vle16.v v8, (a1)
 ; V-NEXT:    vle16.v v9, (a0)
-; V-NEXT:    li a0, -1
 ; V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; V-NEXT:    vslidedown.vi v10, v8, 2
-; V-NEXT:    vwaddu.vv v11, v8, v10
-; V-NEXT:    vwmaccu.vx v11, a0, v10
-; V-NEXT:    vmv.v.i v0, 12
-; V-NEXT:    vnsrl.wi v8, v9, 16
+; V-NEXT:    vnsrl.wi v8, v8, 16
+; V-NEXT:    vnsrl.wi v9, v9, 16
 ; V-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
-; V-NEXT:    vmerge.vvm v8, v8, v11, v0
-; V-NEXT:    vse16.v v8, (a2)
+; V-NEXT:    vslideup.vi v9, v8, 2
+; V-NEXT:    vse16.v v9, (a2)
 ; V-NEXT:    ret
 ;
 ; ZVE32F-LABEL: vnsrl_16_half_two_source:
 ; ZVE32F:       # %bb.0: # %entry
 ; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
 ; ZVE32F-NEXT:    vle16.v v8, (a1)
 ; ZVE32F-NEXT:    vle16.v v9, (a0)
-; ZVE32F-NEXT:    li a0, -1
 ; ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma
-; ZVE32F-NEXT:    vslidedown.vi v10, v8, 2
-; ZVE32F-NEXT:    vwaddu.vv v11, v8, v10
-; ZVE32F-NEXT:    vwmaccu.vx v11, a0, v10
-; ZVE32F-NEXT:    vmv.v.i v0, 12
-; ZVE32F-NEXT:    vnsrl.wi v8, v9, 16
+; ZVE32F-NEXT:    vnsrl.wi v8, v8, 16
+; ZVE32F-NEXT:    vnsrl.wi v9, v9, 16
 ; ZVE32F-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; ZVE32F-NEXT:    vmerge.vvm v8, v8, v11, v0
-; ZVE32F-NEXT:    vse16.v v8, (a2)
+; ZVE32F-NEXT:    vslideup.vi v9, v8, 2
+; ZVE32F-NEXT:    vse16.v v9, (a2)
 ; ZVE32F-NEXT:    ret
 entry:
   %0 = load <4 x half>, ptr %in0, align 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
