Apply suggestions

Created using spr 1.3.6-beta.1

Author: wangpc-pp

clang/lib/CodeGen/CGBuiltin.cpp

@@ -22520,35 +22520,28 @@ Value *CodeGenFunction::EmitRISCVCpuIs(StringRef CPUStr) {
       CGM.CreateRuntimeVariable(StructTy, "__riscv_cpu_model");
   cast<llvm::GlobalValue>(RISCVCPUModel)->setDSOLocal(true);
 
-  auto loadRISCVCPUID = [&](unsigned Index, llvm::Type *ValueTy,
-                            CGBuilderTy &Builder, CodeGenModule &CGM) {
-    llvm::Value *GEPIndices[] = {Builder.getInt32(0),
-                                 llvm::ConstantInt::get(Int32Ty, Index)};
-    Value *Ptr = Builder.CreateInBoundsGEP(StructTy, RISCVCPUModel, GEPIndices);
-    Value *CPUID = Builder.CreateAlignedLoad(
-        ValueTy, Ptr,
-        CharUnits::fromQuantity(ValueTy->getScalarSizeInBits() / 8));
+  auto loadRISCVCPUID = [&](unsigned Index, llvm::Type *ValueTy) {
+    Value *Ptr = Builder.CreateStructGEP(StructTy, RISCVCPUModel, Index);
+    Value *CPUID = Builder.CreateAlignedLoad(ValueTy, Ptr, llvm::MaybeAlign());
     return CPUID;
   };
 
   const llvm::RISCV::CPUModel CPUModel = llvm::RISCV::getCPUModel(CPUStr);
 
   // Compare mvendorid.
-  Value *VendorID = loadRISCVCPUID(0, Int32Ty, Builder, CGM);
-  Value *Result = Builder.CreateICmpEQ(
-      VendorID, llvm::ConstantInt::get(Int32Ty, CPUModel.MVendorID));
+  Value *VendorID = loadRISCVCPUID(0, Int32Ty);
+  Value *Result =
+      Builder.CreateICmpEQ(VendorID, Builder.getInt32(CPUModel.MVendorID));
 
   // Compare marchid.
-  Value *ArchID = loadRISCVCPUID(1, Int64Ty, Builder, CGM);
+  Value *ArchID = loadRISCVCPUID(1, Int64Ty);
   Result = Builder.CreateAnd(
-      Result, Builder.CreateICmpEQ(
-                  ArchID, llvm::ConstantInt::get(Int64Ty, CPUModel.MArchID)));
+      Result, Builder.CreateICmpEQ(ArchID, Builder.getInt64(CPUModel.MArchID)));
 
   // Compare mimplid.
-  Value *ImplID = loadRISCVCPUID(2, Int64Ty, Builder, CGM);
+  Value *ImplID = loadRISCVCPUID(2, Int64Ty);
   Result = Builder.CreateAnd(
-      Result, Builder.CreateICmpEQ(
-                  ImplID, llvm::ConstantInt::get(Int64Ty, CPUModel.MImpID)));
+      Result, Builder.CreateICmpEQ(ImplID, Builder.getInt64(CPUModel.MImpID)));
 
   return Result;
 }

clang/test/CodeGen/RISCV/builtin-cpu-is.c

@@ -7,10 +7,10 @@
 // CHECK-RV64-NEXT:  [[ENTRY:.*:]]
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
-// CHECK-RV64-NEXT:    [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
 // CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854710272
 // CHECK-RV64-NEXT:    [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
-// CHECK-RV64-NEXT:    [[TMP5:%.*]] = load i64, ptr getelementptr inbounds ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
 // CHECK-RV64-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
 // CHECK-RV64-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
 // CHECK-RV64-NEXT:    [[CONV:%.*]] = zext i1 [[TMP7]] to i32
@@ -25,10 +25,10 @@ int test_cpu_is_veyron_v1() {
 // CHECK-RV64-NEXT:  [[ENTRY:.*:]]
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1808
-// CHECK-RV64-NEXT:    [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
 // CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372035378380799
 // CHECK-RV64-NEXT:    [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
-// CHECK-RV64-NEXT:    [[TMP5:%.*]] = load i64, ptr getelementptr inbounds ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
 // CHECK-RV64-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1152921505839391232
 // CHECK-RV64-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
 // CHECK-RV64-NEXT:    [[CONV:%.*]] = zext i1 [[TMP7]] to i32