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[X86][NFC] Hoist out N->getOpcode() used in ReplaceNodeResults (#119494)
Address comment from https://github.com/llvm/llvm-project/pull/119391/files#r1878388699
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‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 18 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -33262,7 +33262,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3326233262
SmallVectorImpl<SDValue>&Results,
3326333263
SelectionDAG &DAG) const {
3326433264
SDLoc dl(N);
33265-
switch (N->getOpcode()) {
33265+
unsigned Opc = N->getOpcode();
33266+
switch (Opc) {
3326633267
default:
3326733268
#ifndef NDEBUG
3326833269
dbgs() << "ReplaceNodeResults: ";
@@ -33358,7 +33359,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3335833359
EVT VT = N->getValueType(0);
3335933360
assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector &&
3336033361
VT == MVT::v2i32 && "Unexpected VT!");
33361-
bool IsSigned = N->getOpcode() == ISD::SMULO;
33362+
bool IsSigned = Opc == ISD::SMULO;
3336233363
unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3336333364
SDValue Op0 = DAG.getNode(ExtOpc, dl, MVT::v2i64, N->getOperand(0));
3336433365
SDValue Op1 = DAG.getNode(ExtOpc, dl, MVT::v2i64, N->getOperand(1));
@@ -33415,7 +33416,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3341533416
Ops[0] = N->getOperand(1);
3341633417
SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWideVT, Ops);
3341733418

33418-
SDValue Res = DAG.getNode(N->getOpcode(), dl, WideVT, InVec0, InVec1);
33419+
SDValue Res = DAG.getNode(Opc, dl, WideVT, InVec0, InVec1);
3341933420
Results.push_back(Res);
3342033421
return;
3342133422
}
@@ -33453,7 +33454,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3345333454
EVT ResVT = getTypeToTransformTo(*DAG.getContext(), VT);
3345433455
SDValue N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Ops0);
3345533456
SDValue N1 = DAG.getConstant(SplatVal, dl, ResVT);
33456-
SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1);
33457+
SDValue Res = DAG.getNode(Opc, dl, ResVT, N0, N1);
3345733458
Results.push_back(Res);
3345833459
}
3345933460
return;
@@ -33574,7 +33575,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3357433575
(InVT == MVT::v4i16 || InVT == MVT::v4i8)){
3357533576
assert(getTypeAction(*DAG.getContext(), InVT) == TypeWidenVector &&
3357633577
"Unexpected type action!");
33577-
assert(N->getOpcode() == ISD::SIGN_EXTEND && "Unexpected opcode");
33578+
assert(Opc == ISD::SIGN_EXTEND && "Unexpected opcode");
3357833579
// Custom split this so we can extend i8/i16->i32 invec. This is better
3357933580
// since sign_extend_inreg i8/i16->i64 requires an extend to i32 using
3358033581
// sra. Then extending from i32 to i64 using pcmpgt. By custom splitting
@@ -33611,7 +33612,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3361133612

3361233613
// Promote the input to 128 bits. Type legalization will turn this into
3361333614
// zext_inreg/sext_inreg.
33614-
In = DAG.getNode(N->getOpcode(), dl, InVT, In);
33615+
In = DAG.getNode(Opc, dl, InVT, In);
3361533616
}
3361633617

3361733618
// Perform custom splitting instead of the two stage extend we would get
@@ -33620,7 +33621,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3362033621
std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
3362133622
assert(isTypeLegal(LoVT) && "Split VT not legal?");
3362233623

33623-
SDValue Lo = getEXTEND_VECTOR_INREG(N->getOpcode(), dl, LoVT, In, DAG);
33624+
SDValue Lo = getEXTEND_VECTOR_INREG(Opc, dl, LoVT, In, DAG);
3362433625

3362533626
// We need to shift the input over by half the number of elements.
3362633627
unsigned NumElts = InVT.getVectorNumElements();
@@ -33630,7 +33631,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3363033631
ShufMask[i] = i + HalfNumElts;
3363133632

3363233633
SDValue Hi = DAG.getVectorShuffle(InVT, dl, In, In, ShufMask);
33633-
Hi = getEXTEND_VECTOR_INREG(N->getOpcode(), dl, HiVT, Hi, DAG);
33634+
Hi = getEXTEND_VECTOR_INREG(Opc, dl, HiVT, Hi, DAG);
3363433635

3363533636
SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
3363633637
Results.push_back(Res);
@@ -33642,8 +33643,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3364233643
case ISD::FP_TO_UINT:
3364333644
case ISD::STRICT_FP_TO_UINT: {
3364433645
bool IsStrict = N->isStrictFPOpcode();
33645-
bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
33646-
N->getOpcode() == ISD::STRICT_FP_TO_SINT;
33646+
bool IsSigned = Opc == ISD::FP_TO_SINT || Opc == ISD::STRICT_FP_TO_SINT;
3364733647
EVT VT = N->getValueType(0);
3364833648
SDValue Src = N->getOperand(IsStrict ? 1 : 0);
3364933649
SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
@@ -33654,13 +33654,13 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3365433654
EVT NVT = VT.isVector() ? VT.changeVectorElementType(MVT::f32) : MVT::f32;
3365533655
if (IsStrict) {
3365633656
Res =
33657-
DAG.getNode(N->getOpcode(), dl, {VT, MVT::Other},
33657+
DAG.getNode(Opc, dl, {VT, MVT::Other},
3365833658
{Chain, DAG.getNode(ISD::STRICT_FP_EXTEND, dl,
3365933659
{NVT, MVT::Other}, {Chain, Src})});
3366033660
Chain = Res.getValue(1);
3366133661
} else {
33662-
Res = DAG.getNode(N->getOpcode(), dl, VT,
33663-
DAG.getNode(ISD::FP_EXTEND, dl, NVT, Src));
33662+
Res =
33663+
DAG.getNode(Opc, dl, VT, DAG.getNode(ISD::FP_EXTEND, dl, NVT, Src));
3366433664
}
3366533665
Results.push_back(Res);
3366633666
if (IsStrict)
@@ -33683,13 +33683,12 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3368333683
}
3368433684

3368533685
if (IsStrict) {
33686-
unsigned Opc =
33687-
IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
33686+
Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
3368833687
Res =
3368933688
DAG.getNode(Opc, dl, {ResVT, MVT::Other}, {N->getOperand(0), Src});
3369033689
Chain = Res.getValue(1);
3369133690
} else {
33692-
unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;
33691+
Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;
3369333692
Res = DAG.getNode(Opc, dl, ResVT, Src);
3369433693
}
3369533694

@@ -33775,7 +33774,6 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3377533774
return;
3377633775
}
3377733776

33778-
unsigned Opc;
3377933777
if (IsStrict)
3378033778
Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
3378133779
else
@@ -33814,7 +33812,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3381433812
if (Src.getValueType() == MVT::v2f32 && IsStrict) {
3381533813
Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32, Src,
3381633814
DAG.getConstantFP(0.0, dl, MVT::v2f32));
33817-
SDValue Res = DAG.getNode(N->getOpcode(), dl, {MVT::v4i32, MVT::Other},
33815+
SDValue Res = DAG.getNode(Opc, dl, {MVT::v4i32, MVT::Other},
3381833816
{N->getOperand(0), Src});
3381933817
Results.push_back(Res);
3382033818
Results.push_back(Res.getValue(1));
@@ -33838,7 +33836,6 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3383833836
std::max(NumElts, 128U / (unsigned)SrcVT.getSizeInBits());
3383933837
MVT VecVT = MVT::getVectorVT(MVT::i64, NumElts);
3384033838
MVT VecInVT = MVT::getVectorVT(SrcVT.getSimpleVT(), SrcElts);
33841-
unsigned Opc = N->getOpcode();
3384233839
if (NumElts != SrcElts) {
3384333840
if (IsStrict)
3384433841
Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
@@ -33892,8 +33889,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3389233889
case ISD::UINT_TO_FP:
3389333890
case ISD::STRICT_UINT_TO_FP: {
3389433891
bool IsStrict = N->isStrictFPOpcode();
33895-
bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
33896-
N->getOpcode() == ISD::STRICT_SINT_TO_FP;
33892+
bool IsSigned = Opc == ISD::SINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP;
3389733893
EVT VT = N->getValueType(0);
3389833894
SDValue Src = N->getOperand(IsStrict ? 1 : 0);
3389933895
if (VT.getVectorElementType() == MVT::f16 && Subtarget.hasFP16() &&
@@ -33987,7 +33983,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3398733983
// FIXME: Should generic type legalizer do this?
3398833984
Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
3398933985
DAG.getConstant(0, dl, MVT::v2i32));
33990-
SDValue Res = DAG.getNode(N->getOpcode(), dl, {MVT::v4f32, MVT::Other},
33986+
SDValue Res = DAG.getNode(Opc, dl, {MVT::v4f32, MVT::Other},
3399133987
{N->getOperand(0), Src});
3399233988
Results.push_back(Res);
3399333989
Results.push_back(Res.getValue(1));

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