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epilkslinder1
epilk
authored and
slinder1
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[AMDGPU][MC] Replace shifted registers in CFI instructions
1 parent 9875b29 commit 314c97a

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10 files changed

+141
-88
lines changed

10 files changed

+141
-88
lines changed

‎llvm/include/llvm/CodeGen/MachineFunction.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1234,6 +1234,10 @@ class LLVM_ABI MachineFunction {
12341234

12351235
[[nodiscard]] unsigned addFrameInst(const MCCFIInstruction &Inst);
12361236

1237+
/// Replace all references to register \param From with register \param To in
1238+
/// frame instructions. Note that .cfi_escape instructions will be left as-is.
1239+
void replaceFrameInstRegister(Register From, Register To);
1240+
12371241
/// Returns a reference to a list of symbols immediately following calls to
12381242
/// _setjmp in the function. Used to construct the longjmp target table used
12391243
/// by Windows Control Flow Guard.

‎llvm/include/llvm/MC/MCDwarf.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -837,6 +837,9 @@ class MCCFIInstruction {
837837
return std::get<EscapeFields>(ExtraFields).Comment;
838838
}
839839
SMLoc getLoc() const { return Loc; }
840+
841+
/// Replaces in place all references to FromReg with ToReg.
842+
void replaceRegister(unsigned FromReg, unsigned ToReg);
840843
};
841844

842845
struct MCDwarfFrameInfo {

‎llvm/lib/CodeGen/MachineFunction.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -336,6 +336,16 @@ MachineFunction::addFrameInst(const MCCFIInstruction &Inst) {
336336
return FrameInstructions.size() - 1;
337337
}
338338

339+
void MachineFunction::replaceFrameInstRegister(Register FromReg,
340+
Register ToReg) {
341+
const MCRegisterInfo *MCRI = Ctx.getRegisterInfo();
342+
unsigned DwarfFromReg = MCRI->getDwarfRegNum(FromReg, false);
343+
unsigned DwarfToReg = MCRI->getDwarfRegNum(ToReg, false);
344+
345+
for (MCCFIInstruction &Inst : FrameInstructions)
346+
Inst.replaceRegister(DwarfFromReg, DwarfToReg);
347+
}
348+
339349
/// This discards all of the MachineBasicBlock numbers and recomputes them.
340350
/// This guarantees that the MBB numbers are sequential, dense, and match the
341351
/// ordering of the blocks within the function. If a specific MachineBasicBlock

‎llvm/lib/MC/MCDwarf.cpp‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1292,6 +1292,39 @@ void MCGenDwarfLabelEntry::Make(MCSymbol *Symbol, MCStreamer *MCOS,
12921292
MCGenDwarfLabelEntry(Name, FileNumber, LineNumber, Label));
12931293
}
12941294

1295+
void MCCFIInstruction::replaceRegister(unsigned FromReg, unsigned ToReg) {
1296+
auto ReplaceReg = [=](unsigned &Reg) {
1297+
if (Reg == FromReg)
1298+
Reg = ToReg;
1299+
};
1300+
auto Visitor = makeVisitor(
1301+
[=](CommonFields &F) {
1302+
ReplaceReg(F.Register);
1303+
ReplaceReg(F.Register2);
1304+
},
1305+
[](EscapeFields &) {}, [](LabelFields &) {},
1306+
[=](RegisterPairFields &F) {
1307+
ReplaceReg(F.Register);
1308+
ReplaceReg(F.Reg1);
1309+
ReplaceReg(F.Reg2);
1310+
},
1311+
[=](VectorRegistersFields &F) {
1312+
ReplaceReg(F.Register);
1313+
for (auto &VRL : F.VectorRegisters)
1314+
ReplaceReg(VRL.Register);
1315+
},
1316+
[=](VectorOffsetFields &F) {
1317+
ReplaceReg(F.Register);
1318+
ReplaceReg(F.MaskRegister);
1319+
},
1320+
[=](VectorRegisterMaskFields &F) {
1321+
ReplaceReg(F.Register);
1322+
ReplaceReg(F.SpillRegister);
1323+
ReplaceReg(F.MaskRegister);
1324+
});
1325+
std::visit(Visitor, ExtraFields);
1326+
}
1327+
12951328
static int getDataAlignmentFactor(MCStreamer &streamer) {
12961329
MCContext &context = streamer.getContext();
12971330
const MCAsmInfo *asmInfo = context.getAsmInfo();

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -386,6 +386,9 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange(
386386
if (RegItr != SpillPhysVGPRs.end()) {
387387
unsigned Idx = std::distance(SpillPhysVGPRs.begin(), RegItr);
388388
SpillPhysVGPRs[Idx] = NewReg;
389+
390+
// For replacing registers used in the CFI instructions.
391+
MF.replaceFrameInstRegister(Reg, NewReg);
389392
}
390393

391394
// The generic `determineCalleeSaves` might have set the old register if it

‎llvm/test/CodeGen/AMDGPU/debug-frame.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2449,7 +2449,7 @@ define hidden void @func_call_clobber() #0 {
24492449
; GFX900-NEXT: v_writelane_b32 v40, s30, 0
24502450
; GFX900-NEXT: s_addk_i32 s32, 0x400
24512451
; GFX900-NEXT: v_writelane_b32 v40, s31, 1
2452-
; GFX900-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
2452+
; GFX900-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
24532453
; GFX900-NEXT: s_getpc_b64 s[16:17]
24542454
; GFX900-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
24552455
; GFX900-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -2723,7 +2723,7 @@ define hidden void @func_call_clobber() #0 {
27232723
; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s30, 0
27242724
; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x400
27252725
; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s31, 1
2726-
; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
2726+
; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
27272727
; GFX90A-V2A-DIS-NEXT: s_getpc_b64 s[16:17]
27282728
; GFX90A-V2A-DIS-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
27292729
; GFX90A-V2A-DIS-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -2997,7 +2997,7 @@ define hidden void @func_call_clobber() #0 {
29972997
; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s30, 0
29982998
; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x400
29992999
; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s31, 1
3000-
; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
3000+
; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
30013001
; GFX90A-V2A-EN-NEXT: s_getpc_b64 s[16:17]
30023002
; GFX90A-V2A-EN-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
30033003
; GFX90A-V2A-EN-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -3240,7 +3240,7 @@ define hidden void @func_call_clobber() #0 {
32403240
; WAVE32-NEXT: v_writelane_b32 v40, s30, 0
32413241
; WAVE32-NEXT: s_addk_i32 s32, 0x200
32423242
; WAVE32-NEXT: v_writelane_b32 v40, s31, 1
3243-
; WAVE32-NEXT: .cfi_llvm_vector_registers 16, 1791, 0, 32, 1791, 1, 32
3243+
; WAVE32-NEXT: .cfi_llvm_vector_registers 16, 1576, 0, 32, 1576, 1, 32
32443244
; WAVE32-NEXT: s_getpc_b64 s[16:17]
32453245
; WAVE32-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
32463246
; WAVE32-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12

‎llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -493,36 +493,36 @@ define weak_odr void @test(i32 %0) !dbg !34 {
493493
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
494494
; CHECK-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 0
495495
; CHECK-NEXT: v_writelane_b32 v41, s34, 0
496-
; CHECK-NEXT: .cfi_llvm_vector_registers 66, 2622, 0, 32
496+
; CHECK-NEXT: .cfi_llvm_vector_registers 66, 2601, 0, 32
497497
; CHECK-NEXT: v_writelane_b32 v41, s35, 1
498-
; CHECK-NEXT: .cfi_llvm_vector_registers 67, 2622, 1, 32
498+
; CHECK-NEXT: .cfi_llvm_vector_registers 67, 2601, 1, 32
499499
; CHECK-NEXT: v_writelane_b32 v41, s36, 2
500-
; CHECK-NEXT: .cfi_llvm_vector_registers 68, 2622, 2, 32
500+
; CHECK-NEXT: .cfi_llvm_vector_registers 68, 2601, 2, 32
501501
; CHECK-NEXT: v_writelane_b32 v41, s37, 3
502-
; CHECK-NEXT: .cfi_llvm_vector_registers 69, 2622, 3, 32
502+
; CHECK-NEXT: .cfi_llvm_vector_registers 69, 2601, 3, 32
503503
; CHECK-NEXT: v_writelane_b32 v41, s38, 4
504-
; CHECK-NEXT: .cfi_llvm_vector_registers 70, 2622, 4, 32
504+
; CHECK-NEXT: .cfi_llvm_vector_registers 70, 2601, 4, 32
505505
; CHECK-NEXT: v_writelane_b32 v41, s39, 5
506-
; CHECK-NEXT: .cfi_llvm_vector_registers 71, 2622, 5, 32
506+
; CHECK-NEXT: .cfi_llvm_vector_registers 71, 2601, 5, 32
507507
; CHECK-NEXT: v_writelane_b32 v41, s48, 6
508-
; CHECK-NEXT: .cfi_llvm_vector_registers 80, 2622, 6, 32
508+
; CHECK-NEXT: .cfi_llvm_vector_registers 80, 2601, 6, 32
509509
; CHECK-NEXT: v_writelane_b32 v41, s49, 7
510-
; CHECK-NEXT: .cfi_llvm_vector_registers 81, 2622, 7, 32
510+
; CHECK-NEXT: .cfi_llvm_vector_registers 81, 2601, 7, 32
511511
; CHECK-NEXT: v_writelane_b32 v41, s50, 8
512-
; CHECK-NEXT: .cfi_llvm_vector_registers 82, 2622, 8, 32
512+
; CHECK-NEXT: .cfi_llvm_vector_registers 82, 2601, 8, 32
513513
; CHECK-NEXT: v_writelane_b32 v41, s51, 9
514-
; CHECK-NEXT: .cfi_llvm_vector_registers 83, 2622, 9, 32
514+
; CHECK-NEXT: .cfi_llvm_vector_registers 83, 2601, 9, 32
515515
; CHECK-NEXT: v_writelane_b32 v41, s52, 10
516-
; CHECK-NEXT: .cfi_llvm_vector_registers 84, 2622, 10, 32
516+
; CHECK-NEXT: .cfi_llvm_vector_registers 84, 2601, 10, 32
517517
; CHECK-NEXT: v_writelane_b32 v41, s53, 11
518-
; CHECK-NEXT: .cfi_llvm_vector_registers 85, 2622, 11, 32
518+
; CHECK-NEXT: .cfi_llvm_vector_registers 85, 2601, 11, 32
519519
; CHECK-NEXT: v_writelane_b32 v41, s54, 12
520-
; CHECK-NEXT: .cfi_llvm_vector_registers 86, 2622, 12, 32
520+
; CHECK-NEXT: .cfi_llvm_vector_registers 86, 2601, 12, 32
521521
; CHECK-NEXT: v_writelane_b32 v41, s55, 13
522-
; CHECK-NEXT: .cfi_llvm_vector_registers 87, 2622, 13, 32
522+
; CHECK-NEXT: .cfi_llvm_vector_registers 87, 2601, 13, 32
523523
; CHECK-NEXT: v_writelane_b32 v41, s30, 14
524524
; CHECK-NEXT: v_writelane_b32 v41, s31, 15
525-
; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2622, 14, 32, 2622, 15, 32
525+
; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2601, 14, 32, 2601, 15, 32
526526
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
527527
; CHECK-NEXT: ;DEBUG_VALUE: dummy:dummy <- undef
528528
; CHECK-NEXT: .Ltmp0:

‎llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ define fastcc i32 @foo() #0 {
1919
; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc
2020
; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
2121
; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31
22-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr127, 0, 32, $vgpr127, 1, 32
22+
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr40, 0, 32, $vgpr40, 1, 32
2323
; CHECK-NEXT: BUNDLE implicit-def $sgpr16_sgpr17, implicit-def $sgpr16, implicit-def $scc, implicit-def $sgpr17 {
2424
; CHECK-NEXT: $sgpr16_sgpr17 = S_GETPC_B64
2525
; CHECK-NEXT: $sgpr16 = S_ADD_U32 internal $sgpr16, target-flags(amdgpu-gotprel32-lo) @bar + 4, implicit-def $scc

‎llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -233,7 +233,7 @@ define hidden void @_ZL3barv() #0 !dbg !1644 {
233233
; CHECK-NEXT: s_add_i32 s32, s32, 0x400
234234
; CHECK-NEXT: v_writelane_b32 v40, s30, 0
235235
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
236-
; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2623, 0, 32, 2623, 1, 32
236+
; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
237237
; CHECK-NEXT: .Ltmp0:
238238
; CHECK-NEXT: .loc 0 31 3 prologue_end ; lane-info.cpp:31:3
239239
; CHECK-NEXT: s_getpc_b64 s[16:17]

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