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[PowerPC] Utilize getReservedRegs to find asm clobberable registers.
1 parent 281d178 commit 31a99e2

12 files changed

+118
-71
lines changed

‎llvm/lib/Target/PowerPC/PPCCallingConv.td‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -423,8 +423,10 @@ def CSR_SVR64_ColdCC_R2_VSRP : CalleeSavedRegs<(add CSR_SVR64_ColdCC_VSRP, X2)>;
423423
def CSR_64_AllRegs_VSRP :
424424
CalleeSavedRegs<(add CSR_64_AllRegs_VSX, CSR_ALL_VSRP)>;
425425

426+
def CSR_AIX64_R2 : CalleeSavedRegs<(add X2, CSR_PPC64)>;
427+
426428
def CSR_AIX64_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;
427429

428-
def CSR_AIX64_R2_VSRP : CalleeSavedRegs<(add CSR_AIX64_VSRP, X2)>;
430+
def CSR_AIX64_R2_VSRP : CalleeSavedRegs<(add X2, CSR_AIX64_VSRP)>;
429431

430432
def CSR_AIX32_VSRP : CalleeSavedRegs<(add CSR_AIX32_Altivec, CSR_VSRP)>;

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3434,6 +3434,8 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
34343434
if (Subtarget.hasAIXShLibTLSModelOpt())
34353435
updateForAIXShLibTLSModelOpt(Model, DAG, getTargetMachine());
34363436

3437+
setUsesTOCBasePtr(DAG);
3438+
34373439
bool IsTLSLocalExecModel = Model == TLSModel::LocalExec;
34383440

34393441
if (IsTLSLocalExecModel || Model == TLSModel::InitialExec) {

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp‎

Lines changed: 18 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -240,7 +240,7 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
240240
if (Subtarget.pairedVectorMemops()) {
241241
if (Subtarget.isAIXABI()) {
242242
if (!TM.getAIXExtendedAltivecABI())
243-
return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
243+
return SaveR2 ? CSR_AIX64_R2_SaveList : CSR_PPC64_SaveList;
244244
return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
245245
}
246246
return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
@@ -250,7 +250,9 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
250250
return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
251251
: CSR_PPC64_Altivec_SaveList;
252252
}
253-
return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
253+
return SaveR2 ? (Subtarget.isAIXABI() ? CSR_AIX64_R2_SaveList
254+
: CSR_PPC64_R2_SaveList)
255+
: CSR_PPC64_SaveList;
254256
}
255257
// 32-bit targets.
256258
if (Subtarget.isAIXABI()) {
@@ -380,23 +382,24 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
380382

381383
markSuperRegs(Reserved, PPC::VRSAVE);
382384

385+
const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
386+
bool UsesTOCBasePtr = FuncInfo->usesTOCBasePtr();
383387
// The SVR4 ABI reserves r2 and r13
384388
if (Subtarget.isSVR4ABI()) {
385389
// We only reserve r2 if we need to use the TOC pointer. If we have no
386390
// explicit uses of the TOC pointer (meaning we're a leaf function with
387391
// no constant-pool loads, etc.) and we have no potential uses inside an
388392
// inline asm block, then we can treat r2 has an ordinary callee-saved
389393
// register.
390-
const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
391-
if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
392-
markSuperRegs(Reserved, PPC::R2); // System-reserved register
393-
markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
394+
if (!TM.isPPC64() || UsesTOCBasePtr || MF.hasInlineAsm())
395+
markSuperRegs(Reserved, PPC::R2); // System-reserved register.
396+
markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register.
394397
}
395398

396-
// Always reserve r2 on AIX for now.
397-
// TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
398399
if (Subtarget.isAIXABI())
399-
markSuperRegs(Reserved, PPC::R2); // System-reserved register
400+
// We only reserve r2 if we need to use the TOC pointer on AIX.
401+
if (!TM.isPPC64() || UsesTOCBasePtr || MF.hasInlineAsm())
402+
markSuperRegs(Reserved, PPC::R2); // System-reserved register.
400403

401404
// On PPC64, r13 is the thread pointer. Never allocate this register.
402405
if (TM.isPPC64())
@@ -441,14 +444,12 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
441444

442445
bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF,
443446
MCRegister PhysReg) const {
444-
// We cannot use getReservedRegs() to find the registers that are not asm
445-
// clobberable because there are some reserved registers which can be
446-
// clobbered by inline asm. For example, when LR is clobbered, the register is
447-
// saved and restored. We will hardcode the registers that are not asm
448-
// cloberable in this function.
449-
450-
// The stack pointer (R1/X1) is not clobberable by inline asm
451-
return PhysReg != PPC::R1 && PhysReg != PPC::X1;
447+
// CTR and LR registers are always reserved, but they are asm clobberable.
448+
if (PhysReg == PPC::CTR || PhysReg == PPC::CTR8 || PhysReg == PPC::LR ||
449+
PhysReg == PPC::LR)
450+
return true;
451+
452+
return !getReservedRegs(MF).test(PhysReg);
452453
}
453454

454455
bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.td‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -341,7 +341,9 @@ def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
341341
// This also helps setting the correct `NumOfGPRsSaved' in traceback table.
342342
let AltOrders = [(add (sub GPRC, R2), R2),
343343
(add (sequence "R%u", 2, 12),
344-
(sequence "R%u", 31, 13), R0, R1, FP, BP)];
344+
(sequence "R%u", 31, 13), R0, R1, FP, BP),
345+
(add (sequence "R%u", 3, 12),
346+
(sequence "R%u", 31, 13), R2, R0, R1, FP, BP)];
345347
let AltOrderSelect = [{
346348
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
347349
}];
@@ -354,7 +356,9 @@ def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
354356
// put it at the end of the list.
355357
let AltOrders = [(add (sub G8RC, X2), X2),
356358
(add (sequence "X%u", 2, 12),
357-
(sequence "X%u", 31, 13), X0, X1, FP8, BP8)];
359+
(sequence "X%u", 31, 13), X0, X1, FP8, BP8),
360+
(add (sequence "X%u", 3, 12),
361+
(sequence "X%u", 31, 13), X2, X0, X1, FP8, BP8)];
358362
let AltOrderSelect = [{
359363
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
360364
}];
@@ -368,7 +372,9 @@ def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)>
368372
// put it at the end of the list.
369373
let AltOrders = [(add (sub GPRC_NOR0, R2), R2),
370374
(add (sequence "R%u", 2, 12),
371-
(sequence "R%u", 31, 13), R1, FP, BP, ZERO)];
375+
(sequence "R%u", 31, 13), R1, FP, BP, ZERO),
376+
(add (sequence "R%u", 3, 12),
377+
(sequence "R%u", 31, 13), R2, R1, FP, BP, ZERO)];
372378
let AltOrderSelect = [{
373379
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
374380
}];
@@ -379,7 +385,9 @@ def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
379385
// put it at the end of the list.
380386
let AltOrders = [(add (sub G8RC_NOX0, X2), X2),
381387
(add (sequence "X%u", 2, 12),
382-
(sequence "X%u", 31, 13), X1, FP8, BP8, ZERO8)];
388+
(sequence "X%u", 31, 13), X1, FP8, BP8, ZERO8),
389+
(add (sequence "X%u", 3, 12),
390+
(sequence "X%u", 31, 13), X2, X1, FP8, BP8, ZERO8)];
383391
let AltOrderSelect = [{
384392
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
385393
}];

‎llvm/lib/Target/PowerPC/PPCSubtarget.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -303,7 +303,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
303303
if (is64BitELFABI())
304304
return 1;
305305
if (isAIXABI())
306-
return 2;
306+
return IsPPC64 ? 3 : 2;
307307
return 0;
308308
}
309309

‎llvm/test/CodeGen/PowerPC/aix-inline-asm-clobber-warning.ll‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
; RUN: llc < %s -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
2+
; RUN: -mcpu=pwr7 -mattr=+altivec -O0 2>&1 | FileCheck %s
3+
4+
; CHECK: warning: inline asm clobber list contains reserved registers: R2
5+
; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
6+
7+
@a = external global i32, align 4
8+
9+
define void @bar() {
10+
store i32 0, ptr @a, align 4
11+
call void asm sideeffect "li 2, 1", "~{r2}"()
12+
ret void
13+
}

‎llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,5 @@ body: |
1717
BLR8 implicit $lr8, implicit undef $rm, implicit $x3, implicit $f1
1818
...
1919
# CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
20-
# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x1
21-
# CHECK-DAG: 4 ]
22-
# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
20+
# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 $x2 ]
21+
# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]

‎llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc-unknown-unkown \
2-
; RUN: -mcpu=pwr7 2>&1 | FileCheck %s
2+
; RUN: -mcpu=pwr7 -O0 2>&1 | FileCheck %s
33
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-unkown \
4-
; RUN: -mcpu=pwr7 2>&1 | FileCheck %s
4+
; RUN: -mcpu=pwr7 -O0 2>&1 | FileCheck %s
55

66
define void @test_r1_clobber() {
77
entry:
@@ -20,3 +20,24 @@ entry:
2020

2121
; CHECK: warning: inline asm clobber list contains reserved registers: X1
2222
; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
23+
24+
; CHECK: warning: inline asm clobber list contains reserved registers: R31
25+
; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
26+
27+
@a = dso_local global i32 100, align 4
28+
define dso_local signext i32 @test_r31_r30_clobber() {
29+
entry:
30+
%retval = alloca i32, align 4
31+
%old = alloca i64, align 8
32+
store i32 0, ptr %retval, align 4
33+
call void asm sideeffect "li 31, 1", "~{r31}"()
34+
call void asm sideeffect "li 30, 1", "~{r30}"()
35+
%0 = call i64 asm sideeffect "mr $0, 31", "=r"()
36+
store i64 %0, ptr %old, align 8
37+
%1 = load i32, ptr @a, align 4
38+
%conv = sext i32 %1 to i64
39+
%2 = alloca i8, i64 %conv, align 16
40+
%3 = load i64, ptr %old, align 8
41+
%conv1 = trunc i64 %3 to i32
42+
ret i32 %conv1
43+
}

‎llvm/test/CodeGen/PowerPC/ldst-16-byte.mir‎

Lines changed: 33 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -8,18 +8,18 @@ alignment: 8
88
tracksRegLiveness: true
99
body: |
1010
bb.0.entry:
11-
liveins: $x3, $x4
11+
liveins: $x5, $x4
1212
; CHECK-LABEL: name: foo
13-
; CHECK: liveins: $x3, $x4
13+
; CHECK: liveins: $x4, $x5
1414
; CHECK-NEXT: {{ $}}
1515
; CHECK-NEXT: early-clobber renamable $g8p3 = LQ 128, $x4
16-
; CHECK-NEXT: $x3 = OR8 $x7, $x7
17-
; CHECK-NEXT: STQ killed renamable $g8p3, 160, $x3
18-
; CHECK-NEXT: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
16+
; CHECK-NEXT: $x5 = OR8 $x7, $x7
17+
; CHECK-NEXT: STQ killed renamable $g8p3, 160, $x5
18+
; CHECK-NEXT: BLR8 implicit $lr8, implicit undef $rm, implicit $x5
1919
%0:g8prc = LQ 128, $x4
20-
$x3 = COPY %0.sub_gp8_x1:g8prc
21-
STQ %0, 160, $x3
22-
BLR8 implicit $lr8, implicit undef $rm, implicit $x3
20+
$x5 = COPY %0.sub_gp8_x1:g8prc
21+
STQ %0, 160, $x5
22+
BLR8 implicit $lr8, implicit undef $rm, implicit $x5
2323
...
2424

2525
---
@@ -73,8 +73,9 @@ body: |
7373
bb.0.entry:
7474
liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12
7575
; CHECK-LABEL: name: spill_g8prc
76-
; CHECK: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
76+
; CHECK: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x2, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
7777
; CHECK-NEXT: {{ $}}
78+
; CHECK-NEXT: STD killed $x2, -152, $x1 :: (store (s64) into %stack.4)
7879
; CHECK-NEXT: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.17, align 16)
7980
; CHECK-NEXT: STD killed $x15, -136, $x1 :: (store (s64) into %fixed-stack.16)
8081
; CHECK-NEXT: STD killed $x16, -128, $x1 :: (store (s64) into %fixed-stack.15, align 16)
@@ -95,42 +96,40 @@ body: |
9596
; CHECK-NEXT: STD killed $x31, -8, $x1 :: (store (s64) into %fixed-stack.0)
9697
; CHECK-NEXT: $x7 = OR8 $x3, $x3
9798
; CHECK-NEXT: renamable $g8p4 = LQARX $x5, $x6
98-
; CHECK-NEXT: STD killed $x8, -160, $x1
99-
; CHECK-NEXT: STD killed $x9, -152, $x1
100-
; CHECK-NEXT: renamable $g8p13 = LQARX $x3, renamable $x4
101-
; CHECK-NEXT: renamable $g8p4 = LQARX $x3, renamable $x4
10299
; CHECK-NEXT: STD killed $x8, -176, $x1
103100
; CHECK-NEXT: STD killed $x9, -168, $x1
104-
; CHECK-NEXT: renamable $g8p4 = LQARX $x3, renamable $x4
101+
; CHECK-NEXT: renamable $g8p1 = LQARX $x3, renamable $x4
102+
; CHECK-NEXT: renamable $g8p4 = LQARX renamable $x7, renamable $x4
105103
; CHECK-NEXT: STD killed $x8, -192, $x1
106104
; CHECK-NEXT: STD killed $x9, -184, $x1
107-
; CHECK-NEXT: renamable $g8p4 = LQARX $x3, renamable $x4
105+
; CHECK-NEXT: renamable $g8p4 = LQARX renamable $x7, renamable $x4
108106
; CHECK-NEXT: STD killed $x8, -208, $x1
109107
; CHECK-NEXT: STD killed $x9, -200, $x1
110-
; CHECK-NEXT: renamable $g8p4 = LQARX $x3, renamable $x4
108+
; CHECK-NEXT: renamable $g8p4 = LQARX renamable $x7, renamable $x4
111109
; CHECK-NEXT: STD killed $x8, -224, $x1
112110
; CHECK-NEXT: STD killed $x9, -216, $x1
113-
; CHECK-NEXT: renamable $g8p10 = LQARX $x3, renamable $x4
114-
; CHECK-NEXT: renamable $g8p9 = LQARX $x3, renamable $x4
115-
; CHECK-NEXT: renamable $g8p8 = LQARX $x3, renamable $x4
116-
; CHECK-NEXT: renamable $g8p7 = LQARX $x3, renamable $x4
117-
; CHECK-NEXT: renamable $g8p15 = LQARX $x3, renamable $x4
118-
; CHECK-NEXT: renamable $g8p11 = LQARX $x3, renamable $x4
119-
; CHECK-NEXT: renamable $g8p12 = LQARX $x3, renamable $x4
120-
; CHECK-NEXT: renamable $g8p14 = LQARX $x3, renamable $x4
121-
; CHECK-NEXT: renamable $g8p5 = LQARX $x3, renamable $x4
122-
; CHECK-NEXT: renamable $g8p4 = LQARX $x3, renamable $x4
123-
; CHECK-NEXT: $x3 = OR8 $x27, $x27
111+
; CHECK-NEXT: renamable $g8p12 = LQARX renamable $x7, renamable $x4
112+
; CHECK-NEXT: renamable $g8p11 = LQARX renamable $x7, renamable $x4
113+
; CHECK-NEXT: renamable $g8p10 = LQARX renamable $x7, renamable $x4
114+
; CHECK-NEXT: renamable $g8p9 = LQARX renamable $x7, renamable $x4
115+
; CHECK-NEXT: renamable $g8p8 = LQARX renamable $x7, renamable $x4
116+
; CHECK-NEXT: renamable $g8p7 = LQARX renamable $x7, renamable $x4
117+
; CHECK-NEXT: renamable $g8p15 = LQARX renamable $x7, renamable $x4
118+
; CHECK-NEXT: renamable $g8p13 = LQARX renamable $x7, renamable $x4
119+
; CHECK-NEXT: renamable $g8p14 = LQARX renamable $x7, renamable $x4
120+
; CHECK-NEXT: renamable $g8p5 = LQARX renamable $x7, renamable $x4
121+
; CHECK-NEXT: renamable $g8p4 = LQARX renamable $x7, renamable $x4
124122
; CHECK-NEXT: STQCX killed renamable $g8p4, renamable $x7, renamable $x4, implicit-def dead $cr0
125123
; CHECK-NEXT: STQCX killed renamable $g8p5, renamable $x7, renamable $x4, implicit-def dead $cr0
126124
; CHECK-NEXT: STQCX killed renamable $g8p14, renamable $x7, renamable $x4, implicit-def dead $cr0
127-
; CHECK-NEXT: STQCX killed renamable $g8p12, renamable $x7, renamable $x4, implicit-def dead $cr0
128-
; CHECK-NEXT: STQCX killed renamable $g8p11, renamable $x7, renamable $x4, implicit-def dead $cr0
125+
; CHECK-NEXT: STQCX killed renamable $g8p13, renamable $x7, renamable $x4, implicit-def dead $cr0
129126
; CHECK-NEXT: STQCX killed renamable $g8p15, renamable $x7, renamable $x4, implicit-def dead $cr0
130127
; CHECK-NEXT: STQCX killed renamable $g8p7, renamable $x7, renamable $x4, implicit-def dead $cr0
131128
; CHECK-NEXT: STQCX killed renamable $g8p8, renamable $x7, renamable $x4, implicit-def dead $cr0
132129
; CHECK-NEXT: STQCX killed renamable $g8p9, renamable $x7, renamable $x4, implicit-def dead $cr0
133130
; CHECK-NEXT: STQCX killed renamable $g8p10, renamable $x7, renamable $x4, implicit-def dead $cr0
131+
; CHECK-NEXT: STQCX killed renamable $g8p11, renamable $x7, renamable $x4, implicit-def dead $cr0
132+
; CHECK-NEXT: STQCX killed renamable $g8p12, renamable $x7, renamable $x4, implicit-def dead $cr0
134133
; CHECK-NEXT: $x8 = LD -224, $x1
135134
; CHECK-NEXT: $x9 = LD -216, $x1
136135
; CHECK-NEXT: STQCX killed renamable $g8p4, renamable $x7, renamable $x4, implicit-def dead $cr0
@@ -140,12 +139,9 @@ body: |
140139
; CHECK-NEXT: $x8 = LD -192, $x1
141140
; CHECK-NEXT: $x9 = LD -184, $x1
142141
; CHECK-NEXT: STQCX killed renamable $g8p4, renamable $x7, renamable $x4, implicit-def dead $cr0
142+
; CHECK-NEXT: STQCX renamable $g8p1, killed renamable $x7, killed renamable $x4, implicit-def dead $cr0
143143
; CHECK-NEXT: $x8 = LD -176, $x1
144144
; CHECK-NEXT: $x9 = LD -168, $x1
145-
; CHECK-NEXT: STQCX killed renamable $g8p4, renamable $x7, renamable $x4, implicit-def dead $cr0
146-
; CHECK-NEXT: STQCX killed renamable $g8p13, killed renamable $x7, killed renamable $x4, implicit-def dead $cr0
147-
; CHECK-NEXT: $x8 = LD -160, $x1
148-
; CHECK-NEXT: $x9 = LD -152, $x1
149145
; CHECK-NEXT: STQCX killed renamable $g8p4, $x5, $x6, implicit-def dead $cr0
150146
; CHECK-NEXT: $x31 = LD -8, $x1 :: (load (s64) from %fixed-stack.0)
151147
; CHECK-NEXT: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
@@ -165,6 +161,7 @@ body: |
165161
; CHECK-NEXT: $x16 = LD -128, $x1 :: (load (s64) from %fixed-stack.15, align 16)
166162
; CHECK-NEXT: $x15 = LD -136, $x1 :: (load (s64) from %fixed-stack.16)
167163
; CHECK-NEXT: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.17, align 16)
164+
; CHECK-NEXT: $x2 = LD -152, $x1 :: (load (s64) from %stack.4)
168165
; CHECK-NEXT: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
169166
%addr0:g8rc_nox0 = COPY $x3
170167
%addr1:g8rc = COPY $x4
@@ -216,10 +213,9 @@ body: |
216213
; CHECK-NEXT: {{ $}}
217214
; CHECK-NEXT: $x4 = OR8 $x16, $x16
218215
; CHECK-NEXT: $x5 = OR8 $x17, $x17
219-
; CHECK-NEXT: $x3 = OR8 $x5, $x5
220-
; CHECK-NEXT: BLR8 implicit $lr8, implicit undef $rm, implicit killed $x3, implicit $x4
216+
; CHECK-NEXT: BLR8 implicit $lr8, implicit undef $rm, implicit $x5, implicit $x4
221217
%0:g8prc = COPY $g8p8
222-
$x3 = COPY %0.sub_gp8_x1:g8prc
218+
$x5 = COPY %0.sub_gp8_x1:g8prc
223219
$x4 = COPY %0.sub_gp8_x0:g8prc
224-
BLR8 implicit $lr8, implicit undef $rm, implicit $x3, implicit $x4
220+
BLR8 implicit $lr8, implicit undef $rm, implicit $x5, implicit $x4
225221
...

‎llvm/test/CodeGen/PowerPC/mflr-store.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,12 +27,12 @@ body: |
2727
; CHECK: $x0 = MFLR8 implicit $lr8
2828
; CHECK-NEXT: STD killed $x0, 16, $x1
2929
; CHECK-NEXT: $x1 = STDU $x1, -32752, $x1
30-
; CHECK-NEXT: BL8 @test_callee, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1, implicit-def $x3
30+
; CHECK-NEXT: BL8 @test_callee, csr_ppc64_r2, implicit-def dead $lr8, implicit $rm, implicit-def $r1, implicit-def $x3
3131
; CHECK-NEXT: $x1 = ADDI8 $x1, 32752
3232
; CHECK-NEXT: $x0 = LD 16, $x1
3333
; CHECK-NEXT: MTLR8 $x0, implicit-def $lr8
3434
; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
35-
BL8 @test_callee, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1, implicit-def $x3
35+
BL8 @test_callee, csr_ppc64_r2, implicit-def dead $lr8, implicit $rm, implicit-def $r1, implicit-def $x3
3636
BLR8 implicit $lr8, implicit $rm, implicit $x3
3737
...
3838

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