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[RISCV] Add test coverage for reassociation with poison generating flags
The 'add' case is correct, the 'or' case is coverage for an upcoming change to fix a bug w.r.t flag preservation.
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llvm/test/CodeGen/RISCV/machine-combiner-mir.ll

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@@ -104,3 +104,45 @@ define double @test_fmadd(double %a0, double %a1, double %a2) {
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%t2 = fdiv double %t1, %t0
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ret double %t2
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}
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define i64 @test_or_flags(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
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; CHECK-LABEL: name: test_or_flags
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY3]], [[COPY2]]
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; CHECK-NEXT: [[OR1:%[0-9]+]]:gpr = disjoint OR [[COPY1]], [[COPY]]
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; CHECK-NEXT: [[OR2:%[0-9]+]]:gpr = disjoint OR killed [[OR]], killed [[OR1]]
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; CHECK-NEXT: $x10 = COPY [[OR2]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%t0 = or i64 %a0, %a1
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%t1 = or disjoint i64 %t0, %a2
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%t2 = or disjoint i64 %t1, %a3
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ret i64 %t2
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}
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define i64 @test_add_flags(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
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; CHECK-LABEL: name: test_add_flags
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY3]], [[COPY2]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY]]
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; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD killed [[ADD]], killed [[ADD1]]
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; CHECK-NEXT: $x10 = COPY [[ADD2]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%t0 = add i64 %a0, %a1
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%t1 = add nsw i64 %t0, %a2
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%t2 = add nuw i64 %t1, %a3
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ret i64 %t2
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}
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