Skip to content

Commit 31ebd1f

Browse files
s-perrons-perron
committed
[SPIRV] Add intrinsic to represent spec constants
SPIR-V has the concept of a specialization constant. See the [SPIR-V spec](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#_specialization_2) for details. This commit adds the ability for the SPIR-V backend to generate the base specialization constants (OpSpecConstant, OpSpecConstantFalse, and OpSpecConstantTrue). This will be used by HLSL.
1 parent eb6577d commit 31ebd1f

File tree

3 files changed

+182
-1
lines changed

3 files changed

+182
-1
lines changed

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,10 @@ let TargetPrefix = "spv" in {
137137
: DefaultAttrsIntrinsic<[llvm_anyptr_ty], [llvm_any_ty, llvm_i32_ty],
138138
[IntrNoMem]>;
139139

140+
def int_spv_get_specialization_constant
141+
: DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_i32_ty, LLVMMatchType<0>],
142+
[IntrNoMem, IntrWillReturn]>;
143+
140144
// Read a value from the image buffer. It does not translate directly to a
141145
// single OpImageRead because the result type is not necessarily a 4 element
142146
// vector.

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 97 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -296,7 +296,22 @@ class SPIRVInstructionSelector : public InstructionSelector {
296296
bool selectImageWriteIntrinsic(MachineInstr &I) const;
297297
bool selectResourceGetPointer(Register &ResVReg, const SPIRVType *ResType,
298298
MachineInstr &I) const;
299-
299+
bool selectGetSpecializationConstant(Register &ResVReg,
300+
const SPIRVType *ResType,
301+
MachineInstr &I) const;
302+
303+
bool buildSpecConstant(llvm::MachineInstr &I, llvm::Register &ResVReg,
304+
llvm::SPIRVType *ResType,
305+
llvm::APInt &DefaultValue) const;
306+
307+
APInt getSpecConstantDefaultValue(llvm::MachineInstr &I) const;
308+
309+
bool buildBoolSpecConstant(Register &ResVReg, const SPIRVType *ResType,
310+
bool DefaultValue, MachineInstr &I) const;
311+
bool buildIntegerSpecConstant(Register &ResVReg, const SPIRVType *ResType,
312+
uint32_t DefaultValue, MachineInstr &I) const;
313+
bool buildIntegerSpecConstant(Register &ResVReg, const SPIRVType *ResType,
314+
uint64_t DefaultValue, MachineInstr &I) const;
300315
// Utilities
301316
std::pair<Register, bool>
302317
buildI32Constant(uint32_t Val, MachineInstr &I,
@@ -3192,6 +3207,9 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
31923207
case Intrinsic::spv_resource_getpointer: {
31933208
return selectResourceGetPointer(ResVReg, ResType, I);
31943209
}
3210+
case Intrinsic::spv_get_specialization_constant: {
3211+
return selectGetSpecializationConstant(ResVReg, ResType, I);
3212+
}
31953213
case Intrinsic::spv_discard: {
31963214
return selectDiscard(ResVReg, ResType, I);
31973215
}
@@ -3309,6 +3327,84 @@ bool SPIRVInstructionSelector::selectResourceGetPointer(
33093327
.constrainAllUses(TII, TRI, RBI);
33103328
}
33113329

3330+
bool SPIRVInstructionSelector::buildBoolSpecConstant(Register &ResVReg,
3331+
const SPIRVType *ResType,
3332+
bool DefaultValue,
3333+
MachineInstr &I) const {
3334+
uint32_t Opc =
3335+
DefaultValue ? SPIRV::OpSpecConstantTrue : SPIRV::OpSpecConstantFalse;
3336+
return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
3337+
.addDef(ResVReg)
3338+
.addUse(GR.getSPIRVTypeID(ResType))
3339+
.constrainAllUses(TII, TRI, RBI);
3340+
}
3341+
3342+
bool SPIRVInstructionSelector::buildIntegerSpecConstant(
3343+
Register &ResVReg, const SPIRVType *ResType, uint32_t DefaultValue,
3344+
MachineInstr &I) const {
3345+
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
3346+
TII.get(SPIRV::OpSpecConstant))
3347+
.addDef(ResVReg)
3348+
.addUse(GR.getSPIRVTypeID(ResType))
3349+
.addImm(DefaultValue)
3350+
.constrainAllUses(TII, TRI, RBI);
3351+
}
3352+
3353+
bool SPIRVInstructionSelector::buildIntegerSpecConstant(
3354+
Register &ResVReg, const SPIRVType *ResType, uint64_t DefaultValue,
3355+
MachineInstr &I) const {
3356+
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
3357+
TII.get(SPIRV::OpSpecConstant))
3358+
.addDef(ResVReg)
3359+
.addUse(GR.getSPIRVTypeID(ResType))
3360+
.addImm(DefaultValue & 0xFFFFFFFF)
3361+
.addImm(DefaultValue >> 32)
3362+
.constrainAllUses(TII, TRI, RBI);
3363+
}
3364+
3365+
bool SPIRVInstructionSelector::selectGetSpecializationConstant(
3366+
Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
3367+
uint32_t Id = foldImm(I.getOperand(2), MRI);
3368+
bool R = false;
3369+
APInt DefaultValue = getSpecConstantDefaultValue(I);
3370+
if (ResType->getOpcode() == SPIRV::OpTypeBool) {
3371+
R = buildBoolSpecConstant(ResVReg, ResType, DefaultValue.getBoolValue(), I);
3372+
} else {
3373+
R = buildSpecConstant(I, ResVReg, ResType, DefaultValue);
3374+
}
3375+
if (!R) {
3376+
return false;
3377+
}
3378+
buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::SpecId, {Id});
3379+
return R;
3380+
}
3381+
3382+
bool SPIRVInstructionSelector::buildSpecConstant(
3383+
llvm::MachineInstr &I, llvm::Register &ResVReg, llvm::SPIRVType *ResType,
3384+
llvm::APInt &DefaultValue) const {
3385+
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
3386+
TII.get(SPIRV::OpSpecConstant))
3387+
.addDef(ResVReg)
3388+
.addUse(GR.getSPIRVTypeID(ResType));
3389+
addNumImm(DefaultValue, MIB);
3390+
return MIB.constrainAllUses(TII, TRI, RBI);
3391+
}
3392+
3393+
APInt SPIRVInstructionSelector::getSpecConstantDefaultValue(
3394+
llvm::MachineInstr &I) const {
3395+
APInt DefaultValue;
3396+
Register DefaultValueReg = I.getOperand(3).getReg();
3397+
auto *D = getDefInstrMaybeConstant(DefaultValueReg, MRI);
3398+
const auto &MO = D->getOperand(1);
3399+
if (MO.isCImm()) {
3400+
DefaultValue = MO.getCImm()->getValue();
3401+
} else {
3402+
assert(MO.isFPImm() && "");
3403+
DefaultValue = MO.getFPImm()->getValue().bitcastToAPInt();
3404+
}
3405+
return DefaultValue;
3406+
}
3407+
33123408
bool SPIRVInstructionSelector::extractSubvector(
33133409
Register &ResVReg, const SPIRVType *ResType, Register &ReadReg,
33143410
MachineInstr &InsertionPoint) const {

‎llvm/test/CodeGen/SPIRV/constant/spec-constant.ll‎

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,81 @@
1+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - | FileCheck %s
2+
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - -filetype=obj | spirv-val %}
3+
4+
; CHECK-DAG: OpDecorate [[bool_const:%[0-9]+]] SpecId 1
5+
; CHECK-DAG: OpDecorate [[short_const:%[0-9]+]] SpecId 2
6+
; CHECK-DAG: OpDecorate [[int_const:%[0-9]+]] SpecId 3
7+
; CHECK-DAG: OpDecorate [[long_const:%[0-9]+]] SpecId 4
8+
; CHECK-DAG: OpDecorate [[float_const:%[0-9]+]] SpecId 8
9+
; CHECK-DAG: OpDecorate [[double_const:%[0-9]+]] SpecId 9
10+
; CHECK-DAG: OpDecorate [[enum_const:%[0-9]+]] SpecId 10
11+
12+
; CHECK-DAG: [[bool_const]] = OpSpecConstantTrue {{%[0-9]+}}
13+
; CHECK-DAG: [[short_const]] = OpSpecConstant {{%[0-9]+}} 4
14+
; CHECK-DAG: [[int_const]] = OpSpecConstant {{%[0-9]+}} 5
15+
; CHECK-DAG: [[long_const]] = OpSpecConstant {{%[0-9]+}} 8
16+
; CHECK-DAG: [[float_const]] = OpSpecConstant {{%[0-9]+}} 1112014848
17+
; CHECK-DAG: [[double_const]] = OpSpecConstant {{%[0-9]+}} 0 1079574528
18+
; CHECK-DAG: [[enum_const]] = OpSpecConstant {{%[0-9]+}} 30
19+
20+
@_ZL10bool_const = internal addrspace(10) global i32 0, align 4
21+
@_ZL11short_const = internal addrspace(10) global i16 0, align 2
22+
@_ZL9int_const = internal addrspace(10) global i32 0, align 4
23+
@_ZL10long_const = internal addrspace(10) global i64 0, align 8
24+
@_ZL11float_const = internal addrspace(10) global float 0.000000e+00, align 4
25+
@_ZL12double_const = internal addrspace(10) global double 0.000000e+00, align 8
26+
@_ZL10enum_const = internal addrspace(10) global i32 0, align 4
27+
28+
; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none)
29+
define void @main() local_unnamed_addr #0 {
30+
entry:
31+
%0 = tail call spir_func i1 @llvm.spv.get.specialization.constant.i1(i32 1, i1 true)
32+
%storedv.i.i = zext i1 %0 to i32
33+
store i32 %storedv.i.i, ptr addrspace(10) @_ZL10bool_const, align 4, !tbaa !3
34+
%1 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL10bool_const)
35+
%2 = tail call spir_func i16 @llvm.spv.get.specialization.constant.i16(i32 2, i16 4)
36+
store i16 %2, ptr addrspace(10) @_ZL11short_const, align 2, !tbaa !7
37+
%3 = tail call ptr @llvm.invariant.start.p10(i64 2, ptr addrspace(10) @_ZL11short_const)
38+
%4 = tail call spir_func i32 @llvm.spv.get.specialization.constant.i32(i32 3, i32 5)
39+
store i32 %4, ptr addrspace(10) @_ZL9int_const, align 4, !tbaa !9
40+
%5 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL9int_const)
41+
%6 = tail call spir_func i64 @llvm.spv.get.specialization.constant.i64(i32 4, i64 8)
42+
store i64 %6, ptr addrspace(10) @_ZL10long_const, align 8, !tbaa !11
43+
%7 = tail call ptr @llvm.invariant.start.p10(i64 8, ptr addrspace(10) @_ZL10long_const)
44+
%14 = tail call reassoc nnan ninf nsz arcp afn spir_func float @llvm.spv.get.specialization.constant.f32(i32 8, float 5.000000e+01)
45+
store float %14, ptr addrspace(10) @_ZL11float_const, align 4, !tbaa !13
46+
%15 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL11float_const)
47+
%16 = tail call reassoc nnan ninf nsz arcp afn spir_func double @llvm.spv.get.specialization.constant.f64(i32 9, double 1.000000e+02)
48+
store double %16, ptr addrspace(10) @_ZL12double_const, align 8, !tbaa !15
49+
%17 = tail call ptr @llvm.invariant.start.p10(i64 8, ptr addrspace(10) @_ZL12double_const)
50+
%18 = tail call spir_func i32 @llvm.spv.get.specialization.constant.i32(i32 10, i32 30)
51+
store i32 %18, ptr addrspace(10) @_ZL10enum_const, align 4, !tbaa !17
52+
%19 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL10enum_const)
53+
ret void
54+
}
55+
56+
attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "approx-func-fp-math"="true" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
57+
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
58+
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
59+
60+
!llvm.module.flags = !{!0, !1}
61+
!llvm.ident = !{!2}
62+
63+
!0 = !{i32 1, !"wchar_size", i32 4}
64+
!1 = !{i32 7, !"frame-pointer", i32 2}
65+
!2 = !{!"clang version 21.0.0git ([email protected]:s-perron/llvm-project.git 060dd85ac525db3606a5ec7ca12ba346a7f075af)"}
66+
!3 = !{!4, !4, i64 0}
67+
!4 = !{!"bool", !5, i64 0}
68+
!5 = !{!"omnipotent char", !6, i64 0}
69+
!6 = !{!"Simple C++ TBAA"}
70+
!7 = !{!8, !8, i64 0}
71+
!8 = !{!"short", !5, i64 0}
72+
!9 = !{!10, !10, i64 0}
73+
!10 = !{!"int", !5, i64 0}
74+
!11 = !{!12, !12, i64 0}
75+
!12 = !{!"long long", !5, i64 0}
76+
!13 = !{!14, !14, i64 0}
77+
!14 = !{!"float", !5, i64 0}
78+
!15 = !{!16, !16, i64 0}
79+
!16 = !{!"double", !5, i64 0}
80+
!17 = !{!18, !18, i64 0}
81+
!18 = !{!"_ZTS1E", !5, i64 0}

0 commit comments

Comments
 (0)