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Update lit tests to address review commits
Remove -verify-machineinstrs Renumber registers
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-74
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2 files changed

+76
-74
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‎llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir‎

Lines changed: 35 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2-
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -verify-machineinstrs --run-pass si-fold-operands %s -o - | FileCheck %s
3-
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -verify-machineinstrs -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE
4-
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE
2+
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s
3+
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE
4+
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE
55

6+
...
67
---
78
name: test
89
tracksRegLiveness: true
@@ -177,51 +178,51 @@ body: |
177178
successors: %bb.1
178179
liveins: $sgpr4_sgpr5
179180
180-
%521:sgpr_64(p4) = COPY $sgpr4_sgpr5
181-
%655:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %521(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
182-
S_BITCMP1_B32 killed %655, 0, implicit-def $scc
183-
%526:sgpr_32 = S_MOV_B32 0
184-
%690:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc
185-
%815:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
186-
%658:sreg_32 = IMPLICIT_DEF
187-
%660:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %690, implicit $exec
188-
%689:sreg_64_xexec = V_CMP_NE_U32_e64 %660, 1, implicit $exec
181+
%0:sgpr_64(p4) = COPY $sgpr4_sgpr5
182+
%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
183+
S_BITCMP1_B32 killed %1, 0, implicit-def $scc
184+
%2:sgpr_32 = S_MOV_B32 0
185+
%3:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc
186+
%4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
187+
%5:sreg_32 = IMPLICIT_DEF
188+
%6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %3, implicit $exec
189+
%7:sreg_64_xexec = V_CMP_NE_U32_e64 %6, 1, implicit $exec
189190
190191
bb.1:
191192
successors: %bb.2, %bb.3
192193
193-
%125:vgpr_32 = PHI %815, %bb.0, %384, %bb.3
194-
%130:sreg_32 = PHI %526, %bb.0, %260, %bb.3
195-
%820:agpr_32 = COPY %125
196-
%659:sreg_64 = S_MOV_B64 -1
197-
$vcc = S_AND_B64 $exec, %689, implicit-def $scc
194+
%8:vgpr_32 = PHI %4, %bb.0, %9, %bb.3
195+
%10:sreg_32 = PHI %2, %bb.0, %11, %bb.3
196+
%12:agpr_32 = COPY %8
197+
%13:sreg_64 = S_MOV_B64 -1
198+
$vcc = S_AND_B64 $exec, %7, implicit-def $scc
198199
S_CBRANCH_VCCNZ %bb.3, implicit $vcc
199200
S_BRANCH %bb.2
200201
201202
bb.2:
202203
successors: %bb.3
203204
204-
%665:sreg_32 = S_OR_B32 %130, 1, implicit-def dead $scc
205-
%667:sreg_32 = S_ASHR_I32 %130, 31, implicit-def dead $scc
206-
%131:sreg_32 = S_AND_B32 killed %667, killed %665, implicit-def dead $scc
207-
%685:vreg_128_align2 = REG_SEQUENCE %125, %subreg.sub0, %815, %subreg.sub1, %815, %subreg.sub2, %815, %subreg.sub3
208-
%671:sreg_64 = REG_SEQUENCE %526, %subreg.sub0, %526, %subreg.sub1
209-
%673:vreg_64_align2 = COPY %671
210-
%675:areg_128_align2 = COPY %685
211-
%672:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %673, %673, killed %675, 0, 0, 0, implicit $mode, implicit $exec
212-
%255:vgpr_32 = COPY %672.sub0
213-
%663:sreg_64 = S_MOV_B64 0
205+
%14:sreg_32 = S_OR_B32 %10, 1, implicit-def dead $scc
206+
%15:sreg_32 = S_ASHR_I32 %10, 31, implicit-def dead $scc
207+
%16:sreg_32 = S_AND_B32 killed %15, killed %14, implicit-def dead $scc
208+
%17:vreg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3
209+
%18:sreg_64 = REG_SEQUENCE %2, %subreg.sub0, %2, %subreg.sub1
210+
%19:vreg_64_align2 = COPY %18
211+
%20:areg_128_align2 = COPY %17
212+
%21:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %19, %19, killed %20, 0, 0, 0, implicit $mode, implicit $exec
213+
%22:vgpr_32 = COPY %21.sub0
214+
%23:sreg_64 = S_MOV_B64 0
214215
215216
bb.3:
216217
successors: %bb.4, %bb.1
217218
218-
%260:sreg_32 = PHI %658, %bb.1, %131, %bb.2
219-
%821:agpr_32 = PHI %820, %bb.1, %672.sub0, %bb.2
220-
%389:sreg_64_xexec = PHI %659, %bb.1, %663, %bb.2
221-
%384:vgpr_32 = COPY %821
222-
%676:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %389, implicit $exec
223-
%684:sreg_64_xexec = V_CMP_NE_U32_e64 %676, 1, implicit $exec
224-
$vcc = S_AND_B64 $exec, %684, implicit-def $scc
219+
%11:sreg_32 = PHI %5, %bb.1, %16, %bb.2
220+
%24:agpr_32 = PHI %12, %bb.1, %21.sub0, %bb.2
221+
%25:sreg_64_xexec = PHI %13, %bb.1, %23, %bb.2
222+
%9:vgpr_32 = COPY %24
223+
%26:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %25, implicit $exec
224+
%27:sreg_64_xexec = V_CMP_NE_U32_e64 %26, 1, implicit $exec
225+
$vcc = S_AND_B64 $exec, %27, implicit-def $scc
225226
S_CBRANCH_VCCNZ %bb.1, implicit $vcc
226227
S_BRANCH %bb.4
227228

‎llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir‎

Lines changed: 41 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2-
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -verify-machineinstrs --run-pass si-fold-operands %s -o - | FileCheck %s
3-
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -verify-machineinstrs -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE
4-
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE
2+
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s
3+
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE
4+
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE
55

6+
...
67
---
78
name: test
89
tracksRegLiveness: true
@@ -132,50 +133,50 @@ body: |
132133
; GFX908-COALESCE-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[V_PACK_B32_F16_e64_]], [[S_MOV_B32_]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8)
133134
; GFX908-COALESCE-NEXT: S_ENDPGM 0
134135
bb.0:
135-
successors: %bb.1, %bb.3
136+
successors: %bb.2, %bb.1
136137
liveins: $sgpr4_sgpr5
137138
138-
%259:sgpr_64(p4) = COPY $sgpr4_sgpr5
139-
%392:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %259(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
140-
%264:sgpr_32 = S_MOV_B32 0
141-
S_BITCMP0_B32 killed %392, 0, implicit-def $scc
142-
S_CBRANCH_SCC0 %bb.1, implicit $scc
143-
144-
bb.3:
145-
successors: %bb.2
146-
147-
%316:sgpr_32 = COPY %264
148-
%484:vgpr_32 = COPY %316, implicit $exec
149-
S_BRANCH %bb.2
139+
%0:sgpr_64(p4) = COPY $sgpr4_sgpr5
140+
%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
141+
%2:sgpr_32 = S_MOV_B32 0
142+
S_BITCMP0_B32 killed %1, 0, implicit-def $scc
143+
S_CBRANCH_SCC0 %bb.2, implicit $scc
150144
151145
bb.1:
152-
successors: %bb.2
146+
successors: %bb.3
153147
154-
%396:sgpr_32 = S_MOV_B32 0
155-
%424:vgpr_32 = COPY %396
156-
%425:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %424, implicit $exec
157-
%427:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %424, implicit $exec
158-
%429:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %424, implicit $exec
159-
%431:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %424, implicit $exec
160-
%403:areg_128_align2 = REG_SEQUENCE %425, %subreg.sub0, %427, %subreg.sub1, %429, %subreg.sub2, %431, %subreg.sub3
161-
%399:sreg_64 = REG_SEQUENCE %396, %subreg.sub0, %396, %subreg.sub1
162-
%401:vreg_64_align2 = COPY %399
163-
%400:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %401, %401, killed %403, 0, 0, 0, implicit $mode, implicit $exec
164-
%404:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %401, %401, killed %400, 0, 0, 0, implicit $mode, implicit $exec
165-
%407:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %401, %401, killed %404, 0, 0, 0, implicit $mode, implicit $exec
166-
%410:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %401, %401, killed %407, 0, 0, 0, implicit $mode, implicit $exec
167-
%48:vgpr_32 = COPY %410.sub0
168-
%52:vgpr_32 = COPY %48
148+
%3:sgpr_32 = COPY %2
149+
%4:vgpr_32 = COPY %3, implicit $exec
150+
S_BRANCH %bb.3
169151
170152
bb.2:
171-
%180:vgpr_32 = PHI %484, %bb.3, %52, %bb.1
172-
%413:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, %180, 0, 0, implicit $mode, implicit $exec
173-
%415:vgpr_32 = nofpexcept V_PACK_B32_F16_e64 0, killed %413, 0, %264, 0, 0, implicit $mode, implicit $exec
174-
%423:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
175-
%422:vreg_64_align2 = REG_SEQUENCE %415, %subreg.sub0, killed %423, %subreg.sub1
176-
%419:sgpr_128 = REG_SEQUENCE %264, %subreg.sub0, %264, %subreg.sub1, %264, %subreg.sub2, %264, %subreg.sub3
177-
%420:vreg_64_align2 = COPY %422
178-
BUFFER_STORE_DWORDX2_OFFSET_exact killed %420, killed %419, %264, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8)
153+
successors: %bb.3
154+
155+
%5:sgpr_32 = S_MOV_B32 0
156+
%6:vgpr_32 = COPY %5
157+
%7:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec
158+
%8:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec
159+
%9:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec
160+
%10:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec
161+
%11:areg_128_align2 = REG_SEQUENCE %7, %subreg.sub0, %8, %subreg.sub1, %9, %subreg.sub2, %10, %subreg.sub3
162+
%12:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %5, %subreg.sub1
163+
%13:vreg_64_align2 = COPY %12
164+
%14:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %11, 0, 0, 0, implicit $mode, implicit $exec
165+
%15:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %14, 0, 0, 0, implicit $mode, implicit $exec
166+
%16:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %15, 0, 0, 0, implicit $mode, implicit $exec
167+
%17:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %16, 0, 0, 0, implicit $mode, implicit $exec
168+
%18:vgpr_32 = COPY %17.sub0
169+
%19:vgpr_32 = COPY %18
170+
171+
bb.3:
172+
%20:vgpr_32 = PHI %4, %bb.1, %19, %bb.2
173+
%21:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, %20, 0, 0, implicit $mode, implicit $exec
174+
%22:vgpr_32 = nofpexcept V_PACK_B32_F16_e64 0, killed %21, 0, %2, 0, 0, implicit $mode, implicit $exec
175+
%23:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
176+
%24:vreg_64_align2 = REG_SEQUENCE %22, %subreg.sub0, killed %23, %subreg.sub1
177+
%25:sgpr_128 = REG_SEQUENCE %2, %subreg.sub0, %2, %subreg.sub1, %2, %subreg.sub2, %2, %subreg.sub3
178+
%26:vreg_64_align2 = COPY %24
179+
BUFFER_STORE_DWORDX2_OFFSET_exact killed %26, killed %25, %2, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8)
179180
S_ENDPGM 0
180181
181182
...

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