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1 parent bd1b6f8 commit 32cb8feCopy full SHA for 32cb8fe
llvm/tools/llvm-exegesis/lib/RISCV/RISCVExegesisPostprocessing.cpp
@@ -6,8 +6,8 @@
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//
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//===----------------------------------------------------------------------===//
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// \file
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-// Currently there is only one post-processing we need to do for exegesis:
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-// Assign a physical register to VSETVL's rd if it's not X0 (i.e. VLMAX).
+// This Pass converts some of the virtual register operands in VSETVLI and FRM
+// pseudos into physical registers.
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