We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent fc35194 commit 32e7e7aCopy full SHA for 32e7e7a
llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
@@ -63,13 +63,9 @@ struct ArgDescriptor {
63
64
bool isRegister() const { return std::holds_alternative<MCRegister>(Val); }
65
66
- MCRegister getRegister() const {
67
- return std::get<MCRegister>(Val);
68
- }
+ MCRegister getRegister() const { return std::get<MCRegister>(Val); }
69
70
- unsigned getStackOffset() const {
71
- return std::get<unsigned>(Val);
72
+ unsigned getStackOffset() const { return std::get<unsigned>(Val); }
73
74
unsigned getMask() const {
75
// None of the target SGPRs or VGPRs are expected to have a 'zero' mask.
0 commit comments