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5 files changed

+84
-45
lines changed

5 files changed

+84
-45
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp‎

Lines changed: 32 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88

99
#include "RISCVAsmBackend.h"
1010
#include "RISCVMCExpr.h"
11+
#include "RISCVMCTargetDesc.h"
1112
#include "llvm/ADT/APInt.h"
1213
#include "llvm/MC/MCAsmInfo.h"
1314
#include "llvm/MC/MCAssembler.h"
@@ -171,8 +172,39 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(
171172
}
172173
}
173174

175+
// Given a compressed control flow instruction this function returns
176+
// the expanded instruction.
177+
static unsigned getRelaxedOpcode(unsigned Op) {
178+
switch (Op) {
179+
default:
180+
return Op;
181+
case RISCV::C_BEQZ:
182+
return RISCV::BEQ;
183+
case RISCV::C_BNEZ:
184+
return RISCV::BNE;
185+
case RISCV::C_J:
186+
case RISCV::C_JAL: // fall through.
187+
return RISCV::JAL;
188+
case RISCV::BEQ:
189+
return RISCV::PseudoLongBEQ;
190+
case RISCV::BNE:
191+
return RISCV::PseudoLongBNE;
192+
case RISCV::BLT:
193+
return RISCV::PseudoLongBLT;
194+
case RISCV::BGE:
195+
return RISCV::PseudoLongBGE;
196+
case RISCV::BLTU:
197+
return RISCV::PseudoLongBLTU;
198+
case RISCV::BGEU:
199+
return RISCV::PseudoLongBGEU;
200+
}
201+
}
202+
174203
void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
175204
const MCSubtargetInfo &STI) const {
205+
if (STI.hasFeature(RISCV::FeatureExactAssembly))
206+
return;
207+
176208
MCInst Res;
177209
switch (Inst.getOpcode()) {
178210
default:
@@ -341,37 +373,7 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
341373
return std::make_pair(Expr.evaluateKnownAbsolute(Value, Asm), false);
342374
}
343375

344-
// Given a compressed control flow instruction this function returns
345-
// the expanded instruction.
346-
unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
347-
// Disable relaxation if FeatureExactAssembly
348-
if (STI.hasFeature(RISCV::FeatureExactAssembly))
349-
return Op;
350376

351-
switch (Op) {
352-
default:
353-
return Op;
354-
case RISCV::C_BEQZ:
355-
return RISCV::BEQ;
356-
case RISCV::C_BNEZ:
357-
return RISCV::BNE;
358-
case RISCV::C_J:
359-
case RISCV::C_JAL: // fall through.
360-
return RISCV::JAL;
361-
case RISCV::BEQ:
362-
return RISCV::PseudoLongBEQ;
363-
case RISCV::BNE:
364-
return RISCV::PseudoLongBNE;
365-
case RISCV::BLT:
366-
return RISCV::PseudoLongBLT;
367-
case RISCV::BGE:
368-
return RISCV::PseudoLongBGE;
369-
case RISCV::BLTU:
370-
return RISCV::PseudoLongBLTU;
371-
case RISCV::BGEU:
372-
return RISCV::PseudoLongBGEU;
373-
}
374-
}
375377

376378
bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
377379
const MCSubtargetInfo &STI) const {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,6 @@ class RISCVAsmBackend : public MCAsmBackend {
8181

8282
bool mayNeedRelaxation(const MCInst &Inst,
8383
const MCSubtargetInfo &STI) const override;
84-
unsigned getRelaxedOpcode(unsigned Op) const;
8584

8685
void relaxInstruction(MCInst &Inst,
8786
const MCSubtargetInfo &STI) const override;

‎llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -254,9 +254,7 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
254254
bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
255255
const MCSubtargetInfo &SubtargetInfo) {
256256
MCInst CInst;
257-
bool Res = false;
258-
if (!SubtargetInfo.hasFeature(RISCV::FeatureExactAssembly))
259-
Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
257+
bool Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
260258
if (Res)
261259
++RISCVNumInstrsCompressed;
262260
S.emitInstruction(Res ? CInst : Inst, SubtargetInfo);

‎llvm/test/MC/RISCV/option-exact-inlineasm.ll‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
; RUN: llc -mtriple=riscv32 -mattr=+relax,+c %s --filetype=obj -o - \
2+
; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -M no-aliases -dr - \
3+
; RUN: | FileCheck %s
4+
5+
define i32 @foo(ptr noundef %f) nounwind {
6+
; CHECK-LABEL: <foo>:
7+
; CHECK: auipc ra, 0x0
8+
; CHECK-NEXT: R_RISCV_CALL_PLT undefined
9+
; CHECK-NEXT: jalr ra, 0x0(ra)
10+
; CHECK-NEXT: lw a0, 0x0(a0)
11+
; CHECK-NEXT: c.jr ra
12+
13+
entry:
14+
%0 = tail call i32 asm sideeffect "
15+
.option exact
16+
call undefined@plt
17+
lw $0, ($1)
18+
.option noexact", "=^cr,^cr"(ptr %f)
19+
ret i32 %0
20+
}
21+

‎llvm/test/MC/RISCV/option-exact-relaxation.s‎

Lines changed: 30 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,15 @@
1-
# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+relax %s \
1+
# RUN: llvm-mc -triple riscv32 -show-encoding \
2+
# RUN: -M no-aliases -mattr=+c,+relax %s \
23
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
3-
# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+relax %s \
4-
# RUN: | llvm-objdump --triple=riscv32 --no-show-raw-insn -dr - \
4+
# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c,+relax %s \
5+
# RUN: | llvm-objdump --triple=riscv32 -M no-aliases -dr - \
56
# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
67

7-
# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+relax %s \
8+
# RUN: llvm-mc -triple riscv64 -show-encoding \
9+
# RUN: -M no-aliases -mattr=+c,+relax %s \
810
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
9-
# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+relax %s \
10-
# RUN: | llvm-objdump --triple=riscv64 --no-show-raw-insn -dr - \
11+
# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c,+relax %s \
12+
# RUN: | llvm-objdump --triple=riscv64 -M no-aliases -dr - \
1113
# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
1214

1315
## `.option exact` disables a variety of assembler behaviour:
@@ -19,7 +21,6 @@
1921
## This test only checks the branch and linker relaxation part of this behaviour.
2022

2123

22-
2324
# CHECK-ASM: call undefined
2425
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
2526
# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
@@ -32,10 +33,16 @@ call undefined@plt
3233
# CHECK-ASM: beq a0, a1, undefined
3334
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
3435
# CHECK-OBJDUMP: bne a0, a1, 0x10
35-
# CHECK-OBJDUMP-NEXT: j 0xc
36+
# CHECK-OBJDUMP-NEXT: jal zero, 0xc
3637
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
3738
beq a0, a1, undefined
3839

40+
# CHECK-ASM: c.j undefined
41+
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
42+
# CHECK-OBJDUMP: jal zero, 0x10
43+
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
44+
c.j undefined
45+
3946
# CHECK-ASM: .option exact
4047
.option exact
4148

@@ -50,10 +57,16 @@ call undefined@plt
5057

5158
# CHECK-ASM: beq a0, a1, undefined
5259
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
53-
# CHECK-OBJDUMP: beq a0, a1, 0x18
60+
# CHECK-OBJDUMP: beq a0, a1, 0x1c
5461
# CHECK-OBJDUMP-NEXT: R_RISCV_BRANCH undefined
5562
beq a0, a1, undefined
5663

64+
# CHECK-ASM: c.j undefined
65+
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
66+
# CHECK-OBJDUMP: c.j 0x20
67+
# CHECK-OBJDUMP-NEXT: R_RISCV_RVC_JUMP undefined
68+
c.j undefined
69+
5770
# CHECK-ASM: .option noexact
5871
.option noexact
5972

@@ -68,7 +81,13 @@ call undefined@plt
6881

6982
# CHECK-ASM: beq a0, a1, undefined
7083
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
71-
# CHECK-OBJDUMP: bne a0, a1, 0x2c
72-
# CHECK-OBJDUMP-NEXT: j 0x28
84+
# CHECK-OBJDUMP: bne a0, a1, 0x32
85+
# CHECK-OBJDUMP-NEXT: jal zero, 0x2e
7386
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
7487
beq a0, a1, undefined
88+
89+
# CHECK-ASM: c.j undefined
90+
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
91+
# CHECK-OBJDUMP: jal zero, 0x32
92+
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
93+
c.j undefined

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