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1 parent b88dfb0 commit 3337757Copy full SHA for 3337757
clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -1836,10 +1836,6 @@ mlir::LogicalResult CIRToLLVMVecInsertOpLowering::matchAndRewrite(
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mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite(
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cir::VecCmpOp op, OpAdaptor adaptor,
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mlir::ConversionPatternRewriter &rewriter) const {
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- assert(mlir::isa<cir::VectorType>(op.getType()) &&
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- mlir::isa<cir::VectorType>(op.getLhs().getType()) &&
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- mlir::isa<cir::VectorType>(op.getRhs().getType()) &&
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- "Vector compare with non-vector type");
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mlir::Type elementType = elementTypeIfVector(op.getLhs().getType());
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mlir::Value bitResult;
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if (auto intType = mlir::dyn_cast<cir::IntType>(elementType)) {
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