Skip to content

Commit 334a046

Browse files
mcberg2021mcberg2021
authored
[LoopDist] Consider reads and writes together for runtime checks (#145623)
Emit safety guards for ptr accesses when cross partition loads exist which have a corresponding store to the same address in a different partition. This will emit the necessary ptr checks for these accesses. The test case was obtained from SuperTest, which SiFive runs regularly. We enabled LoopDistribution by default in our downstream compiler, this change was part of that enablement.
1 parent eeada0d commit 334a046

File tree

3 files changed

+169
-7
lines changed

3 files changed

+169
-7
lines changed

‎llvm/lib/Analysis/LoopAccessAnalysis.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2404,12 +2404,13 @@ bool MemoryDepChecker::areDepsSafe(const DepCandidates &DepCands,
24042404
SmallVector<Instruction *, 4>
24052405
MemoryDepChecker::getInstructionsForAccess(Value *Ptr, bool IsWrite) const {
24062406
MemAccessInfo Access(Ptr, IsWrite);
2407-
auto &IndexVector = Accesses.find(Access)->second;
2408-
2407+
auto I = Accesses.find(Access);
24092408
SmallVector<Instruction *, 4> Insts;
2410-
transform(IndexVector,
2411-
std::back_inserter(Insts),
2412-
[&](unsigned Idx) { return this->InstMap[Idx]; });
2409+
if (I != Accesses.end()) {
2410+
transform(I->second, std::back_inserter(Insts),
2411+
[&](unsigned Idx) { return this->InstMap[Idx]; });
2412+
}
2413+
24132414
return Insts;
24142415
}
24152416

‎llvm/lib/Transforms/Scalar/LoopDistribute.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -502,8 +502,10 @@ class InstPartitionContainer {
502502
SmallVector<int, 8> PtrToPartitions(N);
503503
for (unsigned I = 0; I < N; ++I) {
504504
Value *Ptr = RtPtrCheck->Pointers[I].PointerValue;
505-
auto Instructions =
506-
LAI.getInstructionsForAccess(Ptr, RtPtrCheck->Pointers[I].IsWritePtr);
505+
auto Instructions = LAI.getInstructionsForAccess(Ptr, /* IsWrite */ true);
506+
auto ReadInstructions =
507+
LAI.getInstructionsForAccess(Ptr, /* IsWrite */ false);
508+
Instructions.append(ReadInstructions.begin(), ReadInstructions.end());
507509

508510
int &Partition = PtrToPartitions[I];
509511
// First set it to uninitialized.

‎llvm/test/Transforms/LoopDistribute/cross-partition-access.ll

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,159 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -aa-pipeline=basic-aa -passes=loop-distribute -enable-loop-distribute -verify-loop-info -verify-dom-info -S %s | FileCheck %s
3+
4+
; Test emit safety guards for ptr access of %a and %c on a cross parition load which
5+
; has a corresponding store to the same address. This ensures that if %a and %c
6+
; overlap in some scenarios, that we execute the original loop for safety reasons.
7+
8+
define dso_local void @_Z13distribution3PiS_S_S_i(ptr nocapture noundef %a, ptr nocapture noundef readonly %b, ptr nocapture noundef %c, ptr nocapture noundef writeonly %d, i64 noundef signext %len) {
9+
; CHECK-LABEL: define dso_local void @_Z13distribution3PiS_S_S_i(
10+
; CHECK-SAME: ptr noundef captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], ptr noundef captures(none) [[C:%.*]], ptr noundef writeonly captures(none) [[D:%.*]], i64 noundef signext [[LEN:%.*]]) {
11+
; CHECK-NEXT: [[ENTRY:.*:]]
12+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[LEN]], 0
13+
; CHECK-NEXT: br i1 [[CMP]], label %[[END:.*]], label %[[FOR_BODY_LVER_CHECK:.*]]
14+
; CHECK: [[FOR_BODY_LVER_CHECK]]:
15+
; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[LEN]], 2
16+
; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP0]]
17+
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[C]], i64 -4
18+
; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[C]], i64 [[TMP0]]
19+
; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP0]]
20+
; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP0]]
21+
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[A]], [[SCEVGEP5]]
22+
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP2]]
23+
; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND1]], [[BOUND0]]
24+
; CHECK-NEXT: [[BOUND07:%.*]] = icmp ult ptr [[A]], [[SCEVGEP3]]
25+
; CHECK-NEXT: [[BOUND18:%.*]] = icmp ult ptr [[D]], [[SCEVGEP2]]
26+
; CHECK-NEXT: [[FOUND_CONFLICT9:%.*]] = and i1 [[BOUND07]], [[BOUND18]]
27+
; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT9]]
28+
; CHECK-NEXT: [[BOUND010:%.*]] = icmp ult ptr [[A]], [[SCEVGEP4]]
29+
; CHECK-NEXT: [[BOUND111:%.*]] = icmp ult ptr [[B]], [[SCEVGEP2]]
30+
; CHECK-NEXT: [[FOUND_CONFLICT12:%.*]] = and i1 [[BOUND010]], [[BOUND111]]
31+
; CHECK-NEXT: [[CONFLICT_RDX13:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT12]]
32+
; CHECK-NEXT: [[BOUND014:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP3]]
33+
; CHECK-NEXT: [[BOUND115:%.*]] = icmp ult ptr [[D]], [[SCEVGEP5]]
34+
; CHECK-NEXT: [[FOUND_CONFLICT16:%.*]] = and i1 [[BOUND014]], [[BOUND115]]
35+
; CHECK-NEXT: [[CONFLICT_RDX17:%.*]] = or i1 [[CONFLICT_RDX13]], [[FOUND_CONFLICT16]]
36+
; CHECK-NEXT: [[BOUND018:%.*]] = icmp ult ptr [[D]], [[SCEVGEP4]]
37+
; CHECK-NEXT: [[BOUND119:%.*]] = icmp ult ptr [[B]], [[SCEVGEP3]]
38+
; CHECK-NEXT: [[FOUND_CONFLICT20:%.*]] = and i1 [[BOUND018]], [[BOUND119]]
39+
; CHECK-NEXT: [[CONFLICT_RDX21:%.*]] = or i1 [[CONFLICT_RDX17]], [[FOUND_CONFLICT20]]
40+
; CHECK-NEXT: br i1 [[CONFLICT_RDX21]], label %[[FOR_BODY_PH_LVER_ORIG:.*]], label %[[FOR_BODY_PH_LDIST1:.*]]
41+
; CHECK: [[FOR_BODY_PH_LVER_ORIG]]:
42+
; CHECK-NEXT: br label %[[FOR_BODY_LVER_ORIG:.*]]
43+
; CHECK: [[FOR_BODY_LVER_ORIG]]:
44+
; CHECK-NEXT: [[IDXPROM_LVER_ORIG:%.*]] = phi i64 [ 0, %[[FOR_BODY_PH_LVER_ORIG]] ], [ [[I6_LVER_ORIG:%.*]], %[[FOR_BODY_LVER_ORIG]] ]
45+
; CHECK-NEXT: [[ARRAYIDX_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IDXPROM_LVER_ORIG]]
46+
; CHECK-NEXT: [[I2_LVER_ORIG:%.*]] = load i32, ptr [[ARRAYIDX_LVER_ORIG]], align 4, !tbaa [[TBAA0:![0-9]+]]
47+
; CHECK-NEXT: [[ADD4_LVER_ORIG:%.*]] = add nsw i32 [[I2_LVER_ORIG]], 1
48+
; CHECK-NEXT: [[ARRAYIDX8_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDXPROM_LVER_ORIG]]
49+
; CHECK-NEXT: store i32 [[ADD4_LVER_ORIG]], ptr [[ARRAYIDX8_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
50+
; CHECK-NEXT: [[I3_LVER_ORIG:%.*]] = getelementptr i32, ptr [[C]], i64 [[IDXPROM_LVER_ORIG]]
51+
; CHECK-NEXT: [[ARRAYIDX17_LVER_ORIG:%.*]] = getelementptr i8, ptr [[I3_LVER_ORIG]], i64 -4
52+
; CHECK-NEXT: [[I4_LVER_ORIG:%.*]] = load i32, ptr [[ARRAYIDX17_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
53+
; CHECK-NEXT: [[SUB18_LVER_ORIG:%.*]] = sub nsw i32 [[ADD4_LVER_ORIG]], [[I4_LVER_ORIG]]
54+
; CHECK-NEXT: store i32 [[SUB18_LVER_ORIG]], ptr [[I3_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
55+
; CHECK-NEXT: [[I5_LVER_ORIG:%.*]] = load i32, ptr [[ARRAYIDX8_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
56+
; CHECK-NEXT: [[ADD27_LVER_ORIG:%.*]] = add nsw i32 [[I5_LVER_ORIG]], 2
57+
; CHECK-NEXT: [[ARRAYIDX31_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[D]], i64 [[IDXPROM_LVER_ORIG]]
58+
; CHECK-NEXT: store i32 [[ADD27_LVER_ORIG]], ptr [[ARRAYIDX31_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
59+
; CHECK-NEXT: [[I6_LVER_ORIG]] = add i64 [[IDXPROM_LVER_ORIG]], 1
60+
; CHECK-NEXT: [[CMP1_NOT_LVER_ORIG:%.*]] = icmp eq i64 [[I6_LVER_ORIG]], [[LEN]]
61+
; CHECK-NEXT: br i1 [[CMP1_NOT_LVER_ORIG]], label %[[END_LOOPEXIT_LOOPEXIT:.*]], label %[[FOR_BODY_LVER_ORIG]], !llvm.loop [[LOOP4:![0-9]+]]
62+
; CHECK: [[FOR_BODY_PH_LDIST1]]:
63+
; CHECK-NEXT: br label %[[FOR_BODY_LDIST1:.*]]
64+
; CHECK: [[FOR_BODY_LDIST1]]:
65+
; CHECK-NEXT: [[IDXPROM_LDIST1:%.*]] = phi i64 [ 0, %[[FOR_BODY_PH_LDIST1]] ], [ [[I6_LDIST1:%.*]], %[[FOR_BODY_LDIST1]] ]
66+
; CHECK-NEXT: [[ARRAYIDX_LDIST1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IDXPROM_LDIST1]]
67+
; CHECK-NEXT: [[I2_LDIST1:%.*]] = load i32, ptr [[ARRAYIDX_LDIST1]], align 4, !tbaa [[TBAA0]], !alias.scope [[META6:![0-9]+]]
68+
; CHECK-NEXT: [[ADD4_LDIST1:%.*]] = add nsw i32 [[I2_LDIST1]], 1
69+
; CHECK-NEXT: [[ARRAYIDX8_LDIST1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDXPROM_LDIST1]]
70+
; CHECK-NEXT: store i32 [[ADD4_LDIST1]], ptr [[ARRAYIDX8_LDIST1]], align 4, !tbaa [[TBAA0]], !alias.scope [[META9:![0-9]+]], !noalias [[META11:![0-9]+]]
71+
; CHECK-NEXT: [[I3_LDIST1:%.*]] = getelementptr i32, ptr [[C]], i64 [[IDXPROM_LDIST1]]
72+
; CHECK-NEXT: [[ARRAYIDX17_LDIST1:%.*]] = getelementptr i8, ptr [[I3_LDIST1]], i64 -4
73+
; CHECK-NEXT: [[I4_LDIST1:%.*]] = load i32, ptr [[ARRAYIDX17_LDIST1]], align 4, !tbaa [[TBAA0]], !alias.scope [[META14:![0-9]+]], !noalias [[META15:![0-9]+]]
74+
; CHECK-NEXT: [[SUB18_LDIST1:%.*]] = sub nsw i32 [[ADD4_LDIST1]], [[I4_LDIST1]]
75+
; CHECK-NEXT: store i32 [[SUB18_LDIST1]], ptr [[I3_LDIST1]], align 4, !tbaa [[TBAA0]], !alias.scope [[META14]], !noalias [[META15]]
76+
; CHECK-NEXT: [[I6_LDIST1]] = add i64 [[IDXPROM_LDIST1]], 1
77+
; CHECK-NEXT: [[CMP1_NOT_LDIST1:%.*]] = icmp eq i64 [[I6_LDIST1]], [[LEN]]
78+
; CHECK-NEXT: br i1 [[CMP1_NOT_LDIST1]], label %[[FOR_BODY_PH:.*]], label %[[FOR_BODY_LDIST1]], !llvm.loop [[LOOP16:![0-9]+]]
79+
; CHECK: [[FOR_BODY_PH]]:
80+
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
81+
; CHECK: [[FOR_BODY]]:
82+
; CHECK-NEXT: [[IDXPROM:%.*]] = phi i64 [ 0, %[[FOR_BODY_PH]] ], [ [[I6:%.*]], %[[FOR_BODY]] ]
83+
; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDXPROM]]
84+
; CHECK-NEXT: [[I5:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4, !tbaa [[TBAA0]], !alias.scope [[META9]], !noalias [[META11]]
85+
; CHECK-NEXT: [[ADD27:%.*]] = add nsw i32 [[I5]], 2
86+
; CHECK-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds i32, ptr [[D]], i64 [[IDXPROM]]
87+
; CHECK-NEXT: store i32 [[ADD27]], ptr [[ARRAYIDX31]], align 4, !tbaa [[TBAA0]], !alias.scope [[META15]], !noalias [[META6]]
88+
; CHECK-NEXT: [[I6]] = add i64 [[IDXPROM]], 1
89+
; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[I6]], [[LEN]]
90+
; CHECK-NEXT: br i1 [[CMP1_NOT]], label %[[END_LOOPEXIT_LOOPEXIT20:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP16]]
91+
; CHECK: [[END_LOOPEXIT_LOOPEXIT]]:
92+
; CHECK-NEXT: br label %[[END_LOOPEXIT:.*]]
93+
; CHECK: [[END_LOOPEXIT_LOOPEXIT20]]:
94+
; CHECK-NEXT: br label %[[END_LOOPEXIT]]
95+
; CHECK: [[END_LOOPEXIT]]:
96+
; CHECK-NEXT: br label %[[END]]
97+
; CHECK: [[END]]:
98+
; CHECK-NEXT: ret void
99+
;
100+
entry:
101+
%cmp = icmp sgt i64 %len, 0
102+
br i1 %cmp, label %end, label %for.body.preheader
103+
104+
for.body.preheader: ; preds = %entry
105+
br label %for.body
106+
107+
for.body: ; preds = %for.body, %for.body.preheader
108+
%indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
109+
%arrayidx = getelementptr inbounds i32, ptr %b, i64 %indvars.iv
110+
%i2 = load i32, ptr %arrayidx, align 4, !tbaa !0
111+
%add4 = add nsw i32 %i2, 1
112+
%arrayidx8 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
113+
store i32 %add4, ptr %arrayidx8, align 4, !tbaa !0
114+
%i3 = getelementptr i32, ptr %c, i64 %indvars.iv
115+
%arrayidx17 = getelementptr i8, ptr %i3, i64 -4
116+
%i4 = load i32, ptr %arrayidx17, align 4, !tbaa !0
117+
%sub18 = sub nsw i32 %add4, %i4
118+
store i32 %sub18, ptr %i3, align 4, !tbaa !0
119+
%i5 = load i32, ptr %arrayidx8, align 4, !tbaa !0
120+
%add27 = add nsw i32 %i5, 2
121+
%arrayidx31 = getelementptr inbounds i32, ptr %d, i64 %indvars.iv
122+
store i32 %add27, ptr %arrayidx31, align 4, !tbaa !0
123+
%indvars.iv.next = add i64 %indvars.iv, 1
124+
%cmp1.not = icmp eq i64 %indvars.iv.next, %len
125+
br i1 %cmp1.not, label %end.loopexit, label %for.body, !llvm.loop !4
126+
127+
end.loopexit: ; preds = %for.body
128+
br label %end
129+
130+
end: ; preds = %end.loopexit, %entry
131+
ret void
132+
}
133+
134+
!0 = !{!1, !1, i64 0}
135+
!1 = !{!"int", !2, i64 0}
136+
!2 = !{!"omnipotent char", !3, i64 0}
137+
!3 = !{!"Simple C++ TBAA"}
138+
!4 = distinct !{!4, !5}
139+
!5 = !{!"llvm.loop.mustprogress"}
140+
141+
;.
142+
; CHECK: [[TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
143+
; CHECK: [[META1]] = !{!"int", [[META2:![0-9]+]], i64 0}
144+
; CHECK: [[META2]] = !{!"omnipotent char", [[META3:![0-9]+]], i64 0}
145+
; CHECK: [[META3]] = !{!"Simple C++ TBAA"}
146+
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]}
147+
; CHECK: [[META5]] = !{!"llvm.loop.mustprogress"}
148+
; CHECK: [[META6]] = !{[[META7:![0-9]+]]}
149+
; CHECK: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]]}
150+
; CHECK: [[META8]] = distinct !{[[META8]], !"LVerDomain"}
151+
; CHECK: [[META9]] = !{[[META10:![0-9]+]]}
152+
; CHECK: [[META10]] = distinct !{[[META10]], [[META8]]}
153+
; CHECK: [[META11]] = !{[[META12:![0-9]+]], [[META13:![0-9]+]], [[META7]]}
154+
; CHECK: [[META12]] = distinct !{[[META12]], [[META8]]}
155+
; CHECK: [[META13]] = distinct !{[[META13]], [[META8]]}
156+
; CHECK: [[META14]] = !{[[META12]]}
157+
; CHECK: [[META15]] = !{[[META13]]}
158+
; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META5]]}
159+
;.

0 commit comments

Comments
 (0)