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[NFC][AMDGPU] Auto generate check lines for some test cases (#146400)
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‎llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll‎

Lines changed: 74 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,21 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
23

3-
; GCN-LABEL: {{^}}and_i1_sext_bool:
4-
; GCN: v_cmp_{{gt|le}}_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
5-
; GCN: v_cndmask_b32_e{{32|64}} [[VAL:v[0-9]+]], 0, v{{[0-9]+}}, [[CC]]
6-
; GCN: store_dword {{.*}}[[VAL]]
7-
; GCN-NOT: v_cndmask_b32_e64 v{{[0-9]+}}, {{0|-1}}, {{0|-1}}
8-
; GCN-NOT: v_and_b32_e32
9-
104
define amdgpu_kernel void @and_i1_sext_bool(ptr addrspace(1) nocapture %arg) {
5+
; GCN-LABEL: and_i1_sext_bool:
6+
; GCN: ; %bb.0: ; %bb
7+
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
8+
; GCN-NEXT: s_mov_b32 s3, 0xf000
9+
; GCN-NEXT: s_mov_b32 s2, 0
10+
; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0
11+
; GCN-NEXT: v_mov_b32_e32 v3, 0
12+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
13+
; GCN-NEXT: buffer_load_dword v4, v[2:3], s[0:3], 0 addr64
14+
; GCN-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
15+
; GCN-NEXT: s_waitcnt vmcnt(0)
16+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
17+
; GCN-NEXT: buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
18+
; GCN-NEXT: s_endpgm
1119
bb:
1220
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
1321
%y = tail call i32 @llvm.amdgcn.workitem.id.y()
@@ -20,112 +28,120 @@ bb:
2028
ret void
2129
}
2230

23-
; GCN-LABEL: {{^}}and_sext_bool_fcmp:
24-
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
25-
; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
26-
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
27-
; GCN-NEXT: s_setpc_b64
2831
define i32 @and_sext_bool_fcmp(float %x, i32 %y) {
32+
; GCN-LABEL: and_sext_bool_fcmp:
33+
; GCN: ; %bb.0:
34+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
35+
; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
36+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
37+
; GCN-NEXT: s_setpc_b64 s[30:31]
2938
%cmp = fcmp oeq float %x, 0.0
3039
%sext = sext i1 %cmp to i32
3140
%and = and i32 %sext, %y
3241
ret i32 %and
3342
}
3443

35-
; GCN-LABEL: {{^}}and_sext_bool_fpclass:
36-
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
37-
; GCN-NEXT: v_mov_b32_e32 [[K:v[0-9]+]], 0x7b
38-
; GCN-NEXT: v_cmp_class_f32_e32 vcc, v0, [[K]]
39-
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
40-
; GCN-NEXT: s_setpc_b64
4144
define i32 @and_sext_bool_fpclass(float %x, i32 %y) {
45+
; GCN-LABEL: and_sext_bool_fpclass:
46+
; GCN: ; %bb.0:
47+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
48+
; GCN-NEXT: v_mov_b32_e32 v2, 0x7b
49+
; GCN-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
50+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
51+
; GCN-NEXT: s_setpc_b64 s[30:31]
4252
%class = call i1 @llvm.is.fpclass(float %x, i32 123)
4353
%sext = sext i1 %class to i32
4454
%and = and i32 %sext, %y
4555
ret i32 %and
4656
}
4757

48-
; GCN-LABEL: {{^}}and_sext_bool_uadd_w_overflow:
49-
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
50-
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
51-
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
52-
; GCN-NEXT: s_setpc_b64
5358
define i32 @and_sext_bool_uadd_w_overflow(i32 %x, i32 %y) {
59+
; GCN-LABEL: and_sext_bool_uadd_w_overflow:
60+
; GCN: ; %bb.0:
61+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
62+
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
63+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
64+
; GCN-NEXT: s_setpc_b64 s[30:31]
5465
%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %y)
5566
%carry = extractvalue { i32, i1 } %uadd, 1
5667
%sext = sext i1 %carry to i32
5768
%and = and i32 %sext, %y
5869
ret i32 %and
5970
}
6071

61-
; GCN-LABEL: {{^}}and_sext_bool_usub_w_overflow:
62-
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
63-
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
64-
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
65-
; GCN-NEXT: s_setpc_b64
6672
define i32 @and_sext_bool_usub_w_overflow(i32 %x, i32 %y) {
73+
; GCN-LABEL: and_sext_bool_usub_w_overflow:
74+
; GCN: ; %bb.0:
75+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
76+
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
77+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
78+
; GCN-NEXT: s_setpc_b64 s[30:31]
6779
%uadd = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %x, i32 %y)
6880
%carry = extractvalue { i32, i1 } %uadd, 1
6981
%sext = sext i1 %carry to i32
7082
%and = and i32 %sext, %y
7183
ret i32 %and
7284
}
7385

74-
; GCN-LABEL: {{^}}and_sext_bool_sadd_w_overflow:
75-
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
76-
; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
77-
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v0, v1
78-
; GCN-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
79-
; GCN-NEXT: s_xor_b64 vcc, vcc, s[4:5]
80-
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
81-
; GCN-NEXT: s_setpc_b64
8286
define i32 @and_sext_bool_sadd_w_overflow(i32 %x, i32 %y) {
87+
; GCN-LABEL: and_sext_bool_sadd_w_overflow:
88+
; GCN: ; %bb.0:
89+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
90+
; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
91+
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v0, v1
92+
; GCN-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
93+
; GCN-NEXT: s_xor_b64 vcc, vcc, s[4:5]
94+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
95+
; GCN-NEXT: s_setpc_b64 s[30:31]
8396
%uadd = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %x, i32 %y)
8497
%carry = extractvalue { i32, i1 } %uadd, 1
8598
%sext = sext i1 %carry to i32
8699
%and = and i32 %sext, %y
87100
ret i32 %and
88101
}
89102

90-
; GCN-LABEL: {{^}}and_sext_bool_ssub_w_overflow:
91-
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
92-
; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
93-
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v0, v1
94-
; GCN-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
95-
; GCN-NEXT: s_xor_b64 vcc, vcc, s[4:5]
96-
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
97-
; GCN-NEXT: s_setpc_b64
98103
define i32 @and_sext_bool_ssub_w_overflow(i32 %x, i32 %y) {
104+
; GCN-LABEL: and_sext_bool_ssub_w_overflow:
105+
; GCN: ; %bb.0:
106+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
107+
; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
108+
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v0, v1
109+
; GCN-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
110+
; GCN-NEXT: s_xor_b64 vcc, vcc, s[4:5]
111+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
112+
; GCN-NEXT: s_setpc_b64 s[30:31]
99113
%uadd = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %x, i32 %y)
100114
%carry = extractvalue { i32, i1 } %uadd, 1
101115
%sext = sext i1 %carry to i32
102116
%and = and i32 %sext, %y
103117
ret i32 %and
104118
}
105119

106-
; GCN-LABEL: {{^}}and_sext_bool_smul_w_overflow:
107-
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
108-
; GCN-NEXT: v_mul_hi_i32 v2, v0, v1
109-
; GCN-NEXT: v_mul_lo_u32 v0, v0, v1
110-
; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
111-
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, v2, v0
112-
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
113-
; GCN-NEXT: s_setpc_b64
114120
define i32 @and_sext_bool_smul_w_overflow(i32 %x, i32 %y) {
121+
; GCN-LABEL: and_sext_bool_smul_w_overflow:
122+
; GCN: ; %bb.0:
123+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
124+
; GCN-NEXT: v_mul_hi_i32 v2, v0, v1
125+
; GCN-NEXT: v_mul_lo_u32 v0, v0, v1
126+
; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
127+
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, v2, v0
128+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
129+
; GCN-NEXT: s_setpc_b64 s[30:31]
115130
%uadd = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %x, i32 %y)
116131
%carry = extractvalue { i32, i1 } %uadd, 1
117132
%sext = sext i1 %carry to i32
118133
%and = and i32 %sext, %y
119134
ret i32 %and
120135
}
121136

122-
; GCN-LABEL: {{^}}and_sext_bool_umul_w_overflow:
123-
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
124-
; GCN-NEXT: v_mul_hi_u32 v0, v0, v1
125-
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
126-
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
127-
; GCN-NEXT: s_setpc_b64
128137
define i32 @and_sext_bool_umul_w_overflow(i32 %x, i32 %y) {
138+
; GCN-LABEL: and_sext_bool_umul_w_overflow:
139+
; GCN: ; %bb.0:
140+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
141+
; GCN-NEXT: v_mul_hi_u32 v0, v0, v1
142+
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
143+
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
144+
; GCN-NEXT: s_setpc_b64 s[30:31]
129145
%uadd = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
130146
%carry = extractvalue { i32, i1 } %uadd, 1
131147
%sext = sext i1 %carry to i32

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