[RISCV] Prioritize zext.h/zext.w over XTheadBb th.extu.

Fixes #154125.

Author: topperc

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -1691,7 +1691,9 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     // available.
     // Transform (and x, C1)
     //        -> (<bfextract> x, msb, lsb)
-    if (isMask_64(C1) && !isInt<12>(N1C->getSExtValue())) {
+    if (isMask_64(C1) && !isInt<12>(N1C->getSExtValue()) &&
+        !(C1 == 0xffff && Subtarget->hasStdExtZbb()) &&
+        !(C1 == 0xffffffff && Subtarget->hasStdExtZba())) {
       const unsigned Msb = llvm::bit_width(C1) - 1;
       if (tryUnsignedBitfieldExtract(Node, DL, VT, N0, Msb, 0))
         return;

llvm/test/CodeGen/RISCV/rv32xtheadbb.ll

@@ -537,10 +537,15 @@ define i32 @zexth_i32(i32 %a) nounwind {
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    ret
 ;
-; RV32XTHEADBB-LABEL: zexth_i32:
-; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    th.extu a0, a0, 15, 0
-; RV32XTHEADBB-NEXT:    ret
+; RV32XTHEADBB-NOB-LABEL: zexth_i32:
+; RV32XTHEADBB-NOB:       # %bb.0:
+; RV32XTHEADBB-NOB-NEXT:    th.extu a0, a0, 15, 0
+; RV32XTHEADBB-NOB-NEXT:    ret
+;
+; RV32XTHEADBB-B-LABEL: zexth_i32:
+; RV32XTHEADBB-B:       # %bb.0:
+; RV32XTHEADBB-B-NEXT:    zext.h a0, a0
+; RV32XTHEADBB-B-NEXT:    ret
   %and = and i32 %a, 65535
   ret i32 %and
 }
@@ -553,11 +558,17 @@ define i64 @zexth_i64(i64 %a) nounwind {
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
-; RV32XTHEADBB-LABEL: zexth_i64:
-; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    th.extu a0, a0, 15, 0
-; RV32XTHEADBB-NEXT:    li a1, 0
-; RV32XTHEADBB-NEXT:    ret
+; RV32XTHEADBB-NOB-LABEL: zexth_i64:
+; RV32XTHEADBB-NOB:       # %bb.0:
+; RV32XTHEADBB-NOB-NEXT:    th.extu a0, a0, 15, 0
+; RV32XTHEADBB-NOB-NEXT:    li a1, 0
+; RV32XTHEADBB-NOB-NEXT:    ret
+;
+; RV32XTHEADBB-B-LABEL: zexth_i64:
+; RV32XTHEADBB-B:       # %bb.0:
+; RV32XTHEADBB-B-NEXT:    zext.h a0, a0
+; RV32XTHEADBB-B-NEXT:    li a1, 0
+; RV32XTHEADBB-B-NEXT:    ret
   %and = and i64 %a, 65535
   ret i64 %and
 }

llvm/test/CodeGen/RISCV/rv64xtheadbb.ll

@@ -905,10 +905,15 @@ define i32 @zexth_i32(i32 %a) nounwind {
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    ret
 ;
-; RV64XTHEADBB-LABEL: zexth_i32:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    th.extu a0, a0, 15, 0
-; RV64XTHEADBB-NEXT:    ret
+; RV64XTHEADBB-NOB-LABEL: zexth_i32:
+; RV64XTHEADBB-NOB:       # %bb.0:
+; RV64XTHEADBB-NOB-NEXT:    th.extu a0, a0, 15, 0
+; RV64XTHEADBB-NOB-NEXT:    ret
+;
+; RV64XTHEADBB-B-LABEL: zexth_i32:
+; RV64XTHEADBB-B:       # %bb.0:
+; RV64XTHEADBB-B-NEXT:    zext.h a0, a0
+; RV64XTHEADBB-B-NEXT:    ret
   %and = and i32 %a, 65535
   ret i32 %and
 }
@@ -920,10 +925,15 @@ define i64 @zexth_i64(i64 %a) nounwind {
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    ret
 ;
-; RV64XTHEADBB-LABEL: zexth_i64:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    th.extu a0, a0, 15, 0
-; RV64XTHEADBB-NEXT:    ret
+; RV64XTHEADBB-NOB-LABEL: zexth_i64:
+; RV64XTHEADBB-NOB:       # %bb.0:
+; RV64XTHEADBB-NOB-NEXT:    th.extu a0, a0, 15, 0
+; RV64XTHEADBB-NOB-NEXT:    ret
+;
+; RV64XTHEADBB-B-LABEL: zexth_i64:
+; RV64XTHEADBB-B:       # %bb.0:
+; RV64XTHEADBB-B-NEXT:    zext.h a0, a0
+; RV64XTHEADBB-B-NEXT:    ret
   %and = and i64 %a, 65535
   ret i64 %and
 }
@@ -935,10 +945,15 @@ define i64 @zextw_i64(i64 %a) nounwind {
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
-; RV64XTHEADBB-LABEL: zextw_i64:
-; RV64XTHEADBB:       # %bb.0:
-; RV64XTHEADBB-NEXT:    th.extu a0, a0, 31, 0
-; RV64XTHEADBB-NEXT:    ret
+; RV64XTHEADBB-NOB-LABEL: zextw_i64:
+; RV64XTHEADBB-NOB:       # %bb.0:
+; RV64XTHEADBB-NOB-NEXT:    th.extu a0, a0, 31, 0
+; RV64XTHEADBB-NOB-NEXT:    ret
+;
+; RV64XTHEADBB-B-LABEL: zextw_i64:
+; RV64XTHEADBB-B:       # %bb.0:
+; RV64XTHEADBB-B-NEXT:    zext.w a0, a0
+; RV64XTHEADBB-B-NEXT:    ret
   %and = and i64 %a, 4294967295
   ret i64 %and
 }