[TableGen][DecoderEmitter] Resolve a FIXME in emitDecoder (#154649)

As the FIXME says, we might generate the wrong code to decode an
instruction if it had an operand with no encoding bits. An example is
M68k's `MOV16ds` that is defined as follows:

```
dag OutOperandList = (outs MxDRD16:$dst);
dag InOperandList = (ins SRC:$src);
list<Register> Uses = [SR];
string AsmString = "move.w\t$src, $dst"
dag Inst = (descend { 0, 1, 0, 0, 0, 0, 0, 0, 1, 1 },
            (descend { 0, 0, 0 }, (operand "$dst", 3)));
```

The `$src` operand is not encoded, but what we see in the decoder is:
```C++
    tmp = fieldFromInstruction(insn, 0, 3);
    if (!Check(S, DecodeDR16RegisterClass(MI, tmp, Address, Decoder)))
    { return MCDisassembler::Fail; }
    if (!Check(S, DecodeSRCRegisterClass(MI, insn, Address, Decoder)))
    { return MCDisassembler::Fail; }
    return S;
```

This calls DecodeSRCRegisterClass passing it `insn` instead of the value
of a field that doesn't exist. DecodeSRCRegisterClass has an
unconditional llvm_unreachable inside it.

New decoder looks like:
```C++
    tmp = fieldFromInstruction(insn, 0, 3);
    if (!Check(S, DecodeDR16RegisterClass(MI, tmp, Address, Decoder)))
    { return MCDisassembler::Fail; }
    return S;
```

We're still not disassembling this instruction right, but at least we no
longer have to provide a weird operand decoder method that accepts
instruction bits instead of operand bits.

See #154477 for the origins of the FIXME.

Author: s-barannikov

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

@@ -85,12 +85,6 @@ static DecodeStatus DecodeXR32RegisterClass(MCInst &Inst, uint64_t RegNo,
   return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static DecodeStatus DecodeXR32RegisterClass(MCInst &Inst, APInt RegNo,
-                                            uint64_t Address,
-                                            const void *Decoder) {
-  return DecodeRegisterClass(Inst, RegNo.getZExtValue(), Address, Decoder);
-}
-
 static DecodeStatus DecodeXR16RegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
@@ -113,18 +107,6 @@ static DecodeStatus DecodeFPCSCRegisterClass(MCInst &Inst, uint64_t RegNo,
 }
 #define DecodeFPICRegisterClass DecodeFPCSCRegisterClass
 
-static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn,
-                                            uint64_t Address,
-                                            const void *Decoder) {
-  llvm_unreachable("unimplemented");
-}
-
-static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, APInt &Insn,
-                                           uint64_t Address,
-                                           const void *Decoder) {
-  llvm_unreachable("unimplemented");
-}
-
 static DecodeStatus DecodeImm32(MCInst &Inst, uint64_t Imm, uint64_t Address,
                                 const void *Decoder) {
   Inst.addOperand(MCOperand::createImm(M68k::swapWord<uint32_t>(Imm)));

llvm/utils/TableGen/DecoderEmitter.cpp

@@ -1264,21 +1264,9 @@ void FilterChooser::emitDecoder(raw_ostream &OS, indent Indent,
     return;
   }
 
-  for (const OperandInfo &Op : Encoding.getOperands()) {
-    // FIXME: This is broken. If there is an operand that doesn't contribute
-    //   to the encoding, we generate the same code as if the decoder method
-    //   was specified on the encoding. And then we stop, ignoring the rest
-    //   of the operands. M68k disassembler experiences this.
-    if (Op.numFields() == 0 && !Op.Decoder.empty()) {
-      OS << Indent << "if (!Check(S, " << Op.Decoder
-         << "(MI, insn, Address, Decoder))) { "
-         << (Op.HasCompleteDecoder ? "" : "DecodeComplete = false; ")
-         << "return MCDisassembler::Fail; }\n";
-      break;
-    }
-
-    emitBinaryParser(OS, Indent, Op);
-  }
+  for (const OperandInfo &Op : Encoding.getOperands())
+    if (Op.numFields())
+      emitBinaryParser(OS, Indent, Op);
 }
 
 unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders,