Skip to content

Commit 3427cea

Browse files
fixup! improve tests, move check to isCandidate
1 parent 2d6abe3 commit 3427cea

File tree

2 files changed

+20
-9
lines changed

2 files changed

+20
-9
lines changed

llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -961,8 +961,6 @@ static bool isSupportedInstr(const MachineInstr &MI) {
961961
case RISCV::VMSOF_M:
962962
case RISCV::VIOTA_M:
963963
case RISCV::VID_V:
964-
return true;
965-
966964
// Single-Width Floating-Point/Integer Type-Convert Instructions
967965
case RISCV::VFCVT_XU_F_V:
968966
case RISCV::VFCVT_X_F_V:
@@ -987,7 +985,8 @@ static bool isSupportedInstr(const MachineInstr &MI) {
987985
case RISCV::VFNCVT_F_X_W:
988986
case RISCV::VFNCVT_F_F_W:
989987
case RISCV::VFNCVT_ROD_F_F_W:
990-
return MI.getFlags() & MachineInstr::NoFPExcept;
988+
return true;
989+
991990
}
992991

993992
return false;
@@ -1093,6 +1092,11 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
10931092
return false;
10941093
}
10951094

1095+
if (MI.mayRaiseFPException()) {
1096+
LLVM_DEBUG(dbgs() << "Not a candidate because may raise FP exception\n");
1097+
return false;
1098+
}
1099+
10961100
// Some instructions that produce vectors have semantics that make it more
10971101
// difficult to determine whether the VL can be reduced. For example, some
10981102
// instructions, such as reductions, may write lanes past VL to a scalar

llvm/test/CodeGen/RISCV/rvv/vl-opt.mir

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -111,16 +111,23 @@ body: |
111111
%z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1, 3 /* e8 */, 0
112112
...
113113
---
114-
name: vfcvt.x.f.v
114+
name: vfcvt_x_f_v_nofpexcept
115115
body: |
116116
bb.0:
117-
liveins: $x1
118-
; CHECK-LABEL: name: vfcvt.x.f.v
119-
; CHECK: liveins: $x1
120-
; CHECK-NEXT: {{ $}}
121-
; CHECK-NEXT: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, 1, 3 /* e8 */, 0 /* tu, mu */
117+
; CHECK-LABEL: name: vfcvt_x_f_v_nofpexcept
118+
; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, 1, 3 /* e8 */, 0 /* tu, mu */
122119
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
123120
%x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0
124121
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
125122
...
123+
---
124+
name: vfcvt_x_f_v_fpexcept
125+
body: |
126+
bb.0:
127+
; CHECK-LABEL: name: vfcvt_x_f_v_fpexcept
128+
; CHECK: %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */
129+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
130+
%x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0
131+
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
132+
...
126133

0 commit comments

Comments
 (0)