[Xtensa] Minor fixes.

Author: andreisfr

llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp

@@ -171,7 +171,7 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
 
       // Handle special case. The INTERRUPT/INTSET registers use the same
       // encoding, but INTERRUPT used for read and INTSET for write.
-      if ((Reg == Xtensa::INTERRUPT) && (RAType == Xtensa::REGISTER_WRITE)) {
+      if (Reg == Xtensa::INTERRUPT && RAType == Xtensa::REGISTER_WRITE) {
         Reg = Xtensa::INTSET;
       }
 

llvm/lib/Target/Xtensa/XtensaRegisterInfo.td

@@ -217,10 +217,6 @@ def MR01 :  RegisterClass<"Xtensa", [i32], 32, (add M0, M1)>;
 def MR23 :  RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
 def MR   :  RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
 
-//def SR :  RegisterClass<"Xtensa", [i32], 32, (add
-//  LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART,
-//  MEMCTL, VECBASE, MISC0, MISC1, MISC2, MISC3)>;
-
 def SR :  RegisterClass<"Xtensa", [i32], 32, (add
   LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, ACCLO, ACCHI, MR,
   WINDOWBASE, WINDOWSTART, IBREAKENABLE, MEMCTL, DDR, IBREAKA0, IBREAKA1,