[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem

For a simple matmult kernel this heuristic reduces the length of the critical basic
block from 15 to 20 instructions, resulting in a 20% speedup.

[RISCV] Address PR comment

[RISCV] Add !ST->is64Bit() check

Author: PhilippvK

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

@@ -2329,6 +2329,15 @@ unsigned RISCVTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
   return std::max<unsigned>(1U, RegWidth.getFixedValue() / ElemWidth);
 }
 
+TTI::AddressingModeKind
+RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
+                                         ScalarEvolution *SE) const {
+  if (ST->hasVendorXCVmem() && !ST->is64Bit())
+    return TTI::AMK_PostIndexed;
+
+  return BasicTTIImplBase::getPreferredAddressingMode(L, SE);
+}
+
 bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
                                  const TargetTransformInfo::LSRCost &C2) {
   // RISC-V specific here are "instruction number 1st priority".

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

@@ -388,6 +388,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
     llvm_unreachable("unknown register class");
   }
 
+  TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L,
+                                                     ScalarEvolution *SE) const;
+
   unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
     if (Vector)
       return RISCVRegisterClass::VRRC;

llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll

@@ -5,14 +5,15 @@
 define i32 @test_heuristic(ptr %b, i32 %e, i1 %0) {
 ; CHECK-LABEL: test_heuristic:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    add a3, a0, a1
 ; CHECK-NEXT:    andi a2, a2, 1
 ; CHECK-NEXT:  .LBB0_1: # %loop
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    mv a3, a0
+; CHECK-NEXT:    cv.lbu a1, (a3), 1
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    beqz a2, .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %exit
-; CHECK-NEXT:    cv.lbu a0, a1(a3)
+; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
 entry:
   %1 = getelementptr i8, ptr %b, i32 %e