Pre-commit large spills test

Author: lenary

llvm/test/CodeGen/RISCV/zilsd-large-spill.mir

@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+# RUN: llc %s -mtriple=riscv32 -mattr=+zilsd -start-before=prologepilog -o - | FileCheck %s
+
+# We want to make sure eliminateFrameIndex doesn't fold sp+2044 as an offset in
+# a GPR pair spill/reload instruction. When we split the pair spill, we would be
+# unable to add 4 to the immediate without overflowing simm12.
+
+--- |
+  define void @foo() {
+  ; CHECK-LABEL: foo:
+  ; CHECK:       # %bb.0:
+  ; CHECK-NEXT:    addi sp, sp, -2048
+  ; CHECK-NEXT:    addi sp, sp, -32
+  ; CHECK-NEXT:    .cfi_def_cfa_offset 2080
+  ; CHECK-NEXT:    lui t0, 1
+  ; CHECK-NEXT:    add t0, sp, t0
+  ; CHECK-NEXT:    sd a0, -2024(t0) # 8-byte Folded Spill
+  ; CHECK-NEXT:    lui a0, 1
+  ; CHECK-NEXT:    add a0, sp, a0
+  ; CHECK-NEXT:    sd a2, -2032(a0) # 8-byte Folded Spill
+  ; CHECK-NEXT:    lui a0, 1
+  ; CHECK-NEXT:    add a0, sp, a0
+  ; CHECK-NEXT:    sd a4, -2040(a0) # 8-byte Folded Spill
+  ; CHECK-NEXT:    sd a6, 2044(sp) # 8-byte Folded Spill
+  ; CHECK-NEXT:    lui a0, 1
+  ; CHECK-NEXT:    add a0, sp, a0
+  ; CHECK-NEXT:    ld a0, -2024(a0) # 8-byte Folded Reload
+  ; CHECK-NEXT:    lui a0, 1
+  ; CHECK-NEXT:    add a0, sp, a0
+  ; CHECK-NEXT:    ld a2, -2032(a0) # 8-byte Folded Reload
+  ; CHECK-NEXT:    lui a0, 1
+  ; CHECK-NEXT:    add a0, sp, a0
+  ; CHECK-NEXT:    ld a4, -2040(a0) # 8-byte Folded Reload
+  ; CHECK-NEXT:    ld a6, 2044(sp) # 8-byte Folded Reload
+  ; CHECK-NEXT:    addi sp, sp, 2032
+  ; CHECK-NEXT:    addi sp, sp, 48
+  ; CHECK-NEXT:    .cfi_def_cfa_offset 0
+  ; CHECK-NEXT:    ret
+    unreachable
+  }
+...
+---
+name:            foo
+tracksRegLiveness: true
+tracksDebugUserValues: true
+frameInfo:
+  maxAlignment:    4
+stack:
+  - { id: 0, type: spill-slot, size: 8, alignment: 4 }
+  - { id: 1, type: spill-slot, size: 8, alignment: 4 }
+  - { id: 2, type: spill-slot, size: 8, alignment: 4 }
+  - { id: 3, type: spill-slot, size: 4, alignment: 4 }
+  - { id: 4, type: spill-slot, size: 8, alignment: 4 }
+  - { id: 5, type: spill-slot, size: 2028, alignment: 4 }
+machineFunctionInfo:
+  varArgsFrameIndex: 0
+  varArgsSaveSize: 0
+body:             |
+  bb.0:
+    liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+
+    PseudoSD_RV32_OPT killed renamable $x10, killed renamable $x11, %stack.0, 0 :: (store (s64) into %stack.0, align 4)
+    PseudoSD_RV32_OPT killed renamable $x12, killed renamable $x13, %stack.1, 0 :: (store (s64) into %stack.1, align 4)
+    PseudoSD_RV32_OPT killed renamable $x14, killed renamable $x15, %stack.2, 0 :: (store (s64) into %stack.2, align 4)
+    PseudoSD_RV32_OPT killed renamable $x16, killed renamable $x17, %stack.4, 0 :: (store (s64) into %stack.4, align 4)
+    renamable $x10, renamable $x11 = PseudoLD_RV32_OPT %stack.0, 0 :: (load (s64) from %stack.0, align 4)
+    renamable $x12, renamable $x13 = PseudoLD_RV32_OPT %stack.1, 0 :: (load (s64) from %stack.1, align 4)
+    renamable $x14, renamable $x15 = PseudoLD_RV32_OPT %stack.2, 0 :: (load (s64) from %stack.2, align 4)
+    renamable $x16, renamable $x17 = PseudoLD_RV32_OPT %stack.4, 0 :: (load (s64) from %stack.4, align 4)
+    PseudoRET
+
+...