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[InstCombine] Add pre-commit tests. NFC.
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‎llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll‎

Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1698,6 +1698,118 @@ define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
16981698
ret i32 %o2
16991699
}
17001700

1701+
define i32 @loadCombine_4consecutive_mixsize3(ptr %p) {
1702+
; ALL-LABEL: @loadCombine_4consecutive_mixsize3(
1703+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1704+
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
1705+
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1706+
; ALL-NEXT: [[L2:%.*]] = load i16, ptr [[P1]], align 2
1707+
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
1708+
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1709+
; ALL-NEXT: [[E2:%.*]] = zext i16 [[L2]] to i32
1710+
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1711+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1712+
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
1713+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1714+
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
1715+
; ALL-NEXT: ret i32 [[O2]]
1716+
;
1717+
%p1 = getelementptr i8, ptr %p, i32 1
1718+
%p2 = getelementptr i8, ptr %p, i32 3
1719+
%l1 = load i8, ptr %p
1720+
%l2 = load i16, ptr %p1
1721+
%l3 = load i8, ptr %p2
1722+
1723+
%e1 = zext i8 %l1 to i32
1724+
%e2 = zext i16 %l2 to i32
1725+
%e3 = zext i8 %l3 to i32
1726+
1727+
%s2 = shl i32 %e2, 8
1728+
%s3 = shl i32 %e3, 24
1729+
1730+
%o1 = or i32 %e1, %s2
1731+
%o2 = or i32 %o1, %s3
1732+
ret i32 %o2
1733+
}
1734+
1735+
define i16 @loadCombine_mixsize_4bit(ptr %p) {
1736+
; ALL-LABEL: @loadCombine_mixsize_4bit(
1737+
; ALL-NEXT: [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 2
1738+
; ALL-NEXT: [[P2:%.*]] = getelementptr i4, ptr [[P]], i32 3
1739+
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1740+
; ALL-NEXT: [[L2:%.*]] = load i4, ptr [[P1]], align 1
1741+
; ALL-NEXT: [[L3:%.*]] = load i4, ptr [[P2]], align 1
1742+
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i16
1743+
; ALL-NEXT: [[E2:%.*]] = zext i4 [[L2]] to i16
1744+
; ALL-NEXT: [[E3:%.*]] = zext i4 [[L3]] to i16
1745+
; ALL-NEXT: [[S2:%.*]] = shl i16 [[E2]], 8
1746+
; ALL-NEXT: [[S3:%.*]] = shl i16 [[E3]], 12
1747+
; ALL-NEXT: [[O1:%.*]] = or i16 [[E1]], [[S2]]
1748+
; ALL-NEXT: [[O2:%.*]] = or i16 [[O1]], [[S3]]
1749+
; ALL-NEXT: ret i16 [[O2]]
1750+
;
1751+
%p1 = getelementptr i4, ptr %p, i32 2
1752+
%p2 = getelementptr i4, ptr %p, i32 3
1753+
%l1 = load i8, ptr %p
1754+
%l2 = load i4, ptr %p1
1755+
%l3 = load i4, ptr %p2
1756+
1757+
%e1 = zext i8 %l1 to i16
1758+
%e2 = zext i4 %l2 to i16
1759+
%e3 = zext i4 %l3 to i16
1760+
1761+
%s2 = shl i16 %e2, 8
1762+
%s3 = shl i16 %e3, 12
1763+
1764+
%o1 = or i16 %e1, %s2
1765+
%o2 = or i16 %o1, %s3
1766+
ret i16 %o2
1767+
}
1768+
1769+
define i64 @loadCombine_8consecutive_mixsize(ptr %p) {
1770+
; ALL-LABEL: @loadCombine_8consecutive_mixsize(
1771+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
1772+
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2
1773+
; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 4
1774+
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1775+
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1776+
; ALL-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
1777+
; ALL-NEXT: [[L4:%.*]] = load i32, ptr [[P3]], align 4
1778+
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i64
1779+
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i64
1780+
; ALL-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i64
1781+
; ALL-NEXT: [[E4:%.*]] = zext i32 [[L4]] to i64
1782+
; ALL-NEXT: [[S2:%.*]] = shl i64 [[E2]], 8
1783+
; ALL-NEXT: [[S3:%.*]] = shl i64 [[E3]], 16
1784+
; ALL-NEXT: [[S4:%.*]] = shl i64 [[E4]], 32
1785+
; ALL-NEXT: [[O1:%.*]] = or i64 [[E1]], [[S2]]
1786+
; ALL-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S3]]
1787+
; ALL-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S4]]
1788+
; ALL-NEXT: ret i64 [[O3]]
1789+
;
1790+
%p1 = getelementptr i8, ptr %p, i64 1
1791+
%p2 = getelementptr i8, ptr %p, i64 2
1792+
%p3 = getelementptr i8, ptr %p, i64 4
1793+
%l1 = load i8, ptr %p
1794+
%l2 = load i8, ptr %p1
1795+
%l3 = load i16, ptr %p2
1796+
%l4 = load i32, ptr %p3
1797+
1798+
%e1 = zext i8 %l1 to i64
1799+
%e2 = zext i8 %l2 to i64
1800+
%e3 = zext i16 %l3 to i64
1801+
%e4 = zext i32 %l4 to i64
1802+
1803+
%s2 = shl i64 %e2, 8
1804+
%s3 = shl i64 %e3, 16
1805+
%s4 = shl i64 %e4, 32
1806+
1807+
%o1 = or i64 %e1, %s2
1808+
%o2 = or i64 %o1, %s3
1809+
%o3 = or i64 %o2, %s4
1810+
ret i64 %o3
1811+
}
1812+
17011813
define i32 @loadCombine_4consecutive_lower_index_comes_before(ptr %p) {
17021814
; LE-LABEL: @loadCombine_4consecutive_lower_index_comes_before(
17031815
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1

‎llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll‎

Lines changed: 127 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1812,6 +1812,133 @@ define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
18121812
ret i32 %o2
18131813
}
18141814

1815+
define i32 @loadCombine_4consecutive_mixsize3(ptr %p) {
1816+
; ALL-LABEL: @loadCombine_4consecutive_mixsize3(
1817+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1818+
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
1819+
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1820+
; ALL-NEXT: [[L2:%.*]] = load i16, ptr [[P1]], align 2
1821+
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
1822+
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1823+
; ALL-NEXT: [[E2:%.*]] = zext i16 [[L2]] to i32
1824+
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1825+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1826+
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
1827+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1828+
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
1829+
; ALL-NEXT: ret i32 [[O2]]
1830+
;
1831+
%p1 = getelementptr i8, ptr %p, i32 1
1832+
%p2 = getelementptr i8, ptr %p, i32 3
1833+
%l1 = load i8, ptr %p
1834+
%l2 = load i16, ptr %p1
1835+
%l3 = load i8, ptr %p2
1836+
1837+
%e1 = zext i8 %l1 to i32
1838+
%e2 = zext i16 %l2 to i32
1839+
%e3 = zext i8 %l3 to i32
1840+
1841+
%s2 = shl i32 %e2, 8
1842+
%s3 = shl i32 %e3, 24
1843+
1844+
%o1 = or i32 %e1, %s2
1845+
%o2 = or i32 %o1, %s3
1846+
ret i32 %o2
1847+
}
1848+
1849+
define i16 @loadCombine_mixsize_4bit(ptr %p) {
1850+
; ALL-LABEL: @loadCombine_mixsize_4bit(
1851+
; ALL-NEXT: [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 2
1852+
; ALL-NEXT: [[P2:%.*]] = getelementptr i4, ptr [[P]], i32 3
1853+
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1854+
; ALL-NEXT: [[L2:%.*]] = load i4, ptr [[P1]], align 1
1855+
; ALL-NEXT: [[L3:%.*]] = load i4, ptr [[P2]], align 1
1856+
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i16
1857+
; ALL-NEXT: [[E2:%.*]] = zext i4 [[L2]] to i16
1858+
; ALL-NEXT: [[E3:%.*]] = zext i4 [[L3]] to i16
1859+
; ALL-NEXT: [[S2:%.*]] = shl i16 [[E2]], 8
1860+
; ALL-NEXT: [[S3:%.*]] = shl i16 [[E3]], 12
1861+
; ALL-NEXT: [[O1:%.*]] = or i16 [[E1]], [[S2]]
1862+
; ALL-NEXT: [[O2:%.*]] = or i16 [[O1]], [[S3]]
1863+
; ALL-NEXT: ret i16 [[O2]]
1864+
;
1865+
%p1 = getelementptr i4, ptr %p, i32 2
1866+
%p2 = getelementptr i4, ptr %p, i32 3
1867+
%l1 = load i8, ptr %p
1868+
%l2 = load i4, ptr %p1
1869+
%l3 = load i4, ptr %p2
1870+
1871+
%e1 = zext i8 %l1 to i16
1872+
%e2 = zext i4 %l2 to i16
1873+
%e3 = zext i4 %l3 to i16
1874+
1875+
%s2 = shl i16 %e2, 8
1876+
%s3 = shl i16 %e3, 12
1877+
1878+
%o1 = or i16 %e1, %s2
1879+
%o2 = or i16 %o1, %s3
1880+
ret i16 %o2
1881+
}
1882+
1883+
define i64 @loadCombine_8consecutive_mixsize(ptr %p) {
1884+
; LE-LABEL: @loadCombine_8consecutive_mixsize(
1885+
; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 2
1886+
; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 4
1887+
; LE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 1
1888+
; LE-NEXT: [[TMP1:%.*]] = zext i16 [[L1]] to i64
1889+
; LE-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
1890+
; LE-NEXT: [[L4:%.*]] = load i32, ptr [[P3]], align 4
1891+
; LE-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i64
1892+
; LE-NEXT: [[E4:%.*]] = zext i32 [[L4]] to i64
1893+
; LE-NEXT: [[S3:%.*]] = shl i64 [[E3]], 16
1894+
; LE-NEXT: [[S4:%.*]] = shl i64 [[E4]], 32
1895+
; LE-NEXT: [[O2:%.*]] = or i64 [[TMP1]], [[S3]]
1896+
; LE-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S4]]
1897+
; LE-NEXT: ret i64 [[O3]]
1898+
;
1899+
; BE-LABEL: @loadCombine_8consecutive_mixsize(
1900+
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
1901+
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2
1902+
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 4
1903+
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1904+
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1905+
; BE-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
1906+
; BE-NEXT: [[L4:%.*]] = load i32, ptr [[P3]], align 4
1907+
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i64
1908+
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i64
1909+
; BE-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i64
1910+
; BE-NEXT: [[E4:%.*]] = zext i32 [[L4]] to i64
1911+
; BE-NEXT: [[S2:%.*]] = shl i64 [[E2]], 8
1912+
; BE-NEXT: [[S3:%.*]] = shl i64 [[E3]], 16
1913+
; BE-NEXT: [[S4:%.*]] = shl i64 [[E4]], 32
1914+
; BE-NEXT: [[O1:%.*]] = or i64 [[E1]], [[S2]]
1915+
; BE-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S3]]
1916+
; BE-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S4]]
1917+
; BE-NEXT: ret i64 [[O3]]
1918+
;
1919+
%p1 = getelementptr i8, ptr %p, i64 1
1920+
%p2 = getelementptr i8, ptr %p, i64 2
1921+
%p3 = getelementptr i8, ptr %p, i64 4
1922+
%l1 = load i8, ptr %p
1923+
%l2 = load i8, ptr %p1
1924+
%l3 = load i16, ptr %p2
1925+
%l4 = load i32, ptr %p3
1926+
1927+
%e1 = zext i8 %l1 to i64
1928+
%e2 = zext i8 %l2 to i64
1929+
%e3 = zext i16 %l3 to i64
1930+
%e4 = zext i32 %l4 to i64
1931+
1932+
%s2 = shl i64 %e2, 8
1933+
%s3 = shl i64 %e3, 16
1934+
%s4 = shl i64 %e4, 32
1935+
1936+
%o1 = or i64 %e1, %s2
1937+
%o2 = or i64 %o1, %s3
1938+
%o3 = or i64 %o2, %s4
1939+
ret i64 %o3
1940+
}
1941+
18151942
define i32 @loadCombine_4consecutive_lower_index_comes_before(ptr %p) {
18161943
; LE-LABEL: @loadCombine_4consecutive_lower_index_comes_before(
18171944
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1

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