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Revert "fixup! add vsmul to isSupported"
This reverts commit fc5c72c.
1 parent fc5c72c commit 34616c9

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2 files changed

+1
-49
lines changed

2 files changed

+1
-49
lines changed

llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -745,9 +745,6 @@ static bool isSupportedInstr(const MachineInstr &MI) {
745745
case RISCV::VMV_V_I:
746746
case RISCV::VMV_V_X:
747747
case RISCV::VMV_V_V:
748-
// Vector Single-Width Fractional Multiply with Rounding and Saturation
749-
case RISCV::VSMUL_VV:
750-
case RISCV::VSMUL_VX:
751748

752749
// Vector Crypto
753750
case RISCV::VWSLL_VI:
@@ -843,7 +840,7 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
843840
const MCInstrDesc &Desc = MI.getDesc();
844841
if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags))
845842
return false;
846-
if (MI.getNumExplicitDefs() != 1)
843+
if (MI.getNumDefs() != 1)
847844
return false;
848845

849846
// If we're not using VLMAX, then we need to be careful whether we are using

llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll

Lines changed: 0 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -2925,48 +2925,3 @@ define <vscale x 4 x i32> @vid.v(<vscale x 4 x i32> %c, iXLen %vl) {
29252925
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %c, iXLen %vl)
29262926
ret <vscale x 4 x i32> %2
29272927
}
2928-
2929-
define <vscale x 4 x i32> @vsmul_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
2930-
; NOVLOPT-LABEL: vsmul_vv:
2931-
; NOVLOPT: # %bb.0:
2932-
; NOVLOPT-NEXT: csrwi vxrm, 0
2933-
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2934-
; NOVLOPT-NEXT: vsmul.vv v8, v8, v10
2935-
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2936-
; NOVLOPT-NEXT: vadd.vv v8, v8, v10
2937-
; NOVLOPT-NEXT: ret
2938-
;
2939-
; VLOPT-LABEL: vsmul_vv:
2940-
; VLOPT: # %bb.0:
2941-
; VLOPT-NEXT: csrwi vxrm, 0
2942-
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2943-
; VLOPT-NEXT: vsmul.vv v8, v8, v10
2944-
; VLOPT-NEXT: vadd.vv v8, v8, v10
2945-
; VLOPT-NEXT: ret
2946-
%1 = call <vscale x 4 x i32> @llvm.riscv.vsmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)
2947-
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)
2948-
ret <vscale x 4 x i32> %2
2949-
}
2950-
2951-
define <vscale x 4 x i32> @vsmul_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
2952-
; NOVLOPT-LABEL: vsmul_vx:
2953-
; NOVLOPT: # %bb.0:
2954-
; NOVLOPT-NEXT: csrwi vxrm, 0
2955-
; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
2956-
; NOVLOPT-NEXT: vsmul.vx v10, v8, a0
2957-
; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
2958-
; NOVLOPT-NEXT: vadd.vv v8, v10, v8
2959-
; NOVLOPT-NEXT: ret
2960-
;
2961-
; VLOPT-LABEL: vsmul_vx:
2962-
; VLOPT: # %bb.0:
2963-
; VLOPT-NEXT: csrwi vxrm, 0
2964-
; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
2965-
; VLOPT-NEXT: vsmul.vx v10, v8, a0
2966-
; VLOPT-NEXT: vadd.vv v8, v10, v8
2967-
; VLOPT-NEXT: ret
2968-
%1 = call <vscale x 4 x i32> @llvm.riscv.vsmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen 0, iXLen -1)
2969-
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
2970-
ret <vscale x 4 x i32> %2
2971-
}
2972-

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