@@ -2929,14 +2929,16 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
29292929 unsigned selectOp;
29302930 unsigned addOp;
29312931 if (isScalarRes) {
2932- NegOneReg = GR.getOrCreateConstInt (-1 , I, ResType, TII, ZeroAsNull);
2932+ NegOneReg =
2933+ GR.getOrCreateConstInt ((unsigned )-1 , I, ResType, TII, ZeroAsNull);
29332934 Reg0 = GR.getOrCreateConstInt (0 , I, ResType, TII, ZeroAsNull);
29342935 Reg32 = GR.getOrCreateConstInt (32 , I, ResType, TII, ZeroAsNull);
29352936 selectOp = SPIRV::OpSelectSISCond;
29362937 addOp = SPIRV::OpIAddS;
29372938 } else {
29382939 BoolType = GR.getOrCreateSPIRVVectorType (BoolType, count, MIRBuilder);
2939- NegOneReg = GR.getOrCreateConstVector (-1 , I, ResType, TII, ZeroAsNull);
2940+ NegOneReg =
2941+ GR.getOrCreateConstVector ((unsigned )-1 , I, ResType, TII, ZeroAsNull);
29402942 Reg0 = GR.getOrCreateConstVector (0 , I, ResType, TII, ZeroAsNull);
29412943 Reg32 = GR.getOrCreateConstVector (32 , I, ResType, TII, ZeroAsNull);
29422944 selectOp = SPIRV::OpSelectVIVCond;
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