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AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (#117796)
Co-authored-by: Shilei Tian <[email protected]>
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‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

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Original file line numberDiff line numberDiff line change
@@ -420,6 +420,12 @@ def FeatureF16BF16ToFP6BF6ConversionScaleInsts : SubtargetFeature<"f16bf16-to-fp
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"Has f16bf16 to fp6bf6 conversion scale instructions"
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>;
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def FeatureF32ToF16BF16ConversionSRInsts : SubtargetFeature<"f32-to-f16bf16-cvt-sr-insts",
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"HasF32ToF16BF16ConversionSRInsts",
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"true",
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"Has f32 to f16bf16 conversion scale instructions"
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>;
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def FeatureAshrPkInsts : SubtargetFeature<"ashr-pk-insts",
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"HasAshrPkInsts",
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"true",
@@ -438,6 +444,7 @@ def FeatureGFX950Insts : SubtargetFeature<"gfx950-insts",
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FeatureFP4ConversionScaleInsts,
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FeatureFP6BF6ConversionScaleInsts,
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FeatureF16BF16ToFP6BF6ConversionScaleInsts,
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FeatureF32ToF16BF16ConversionSRInsts,
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FeatureMinimum3Maximum3F32,
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FeatureMinimum3Maximum3PKF16
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]
@@ -2504,6 +2511,9 @@ def HasFP6BF6ConversionScaleInsts : Predicate<"Subtarget->hasFP6BF6ConversionSca
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def HasF16BF16ToFP6BF6ConversionScaleInsts : Predicate<"Subtarget->hasF16BF16ToFP6BF6ConversionScaleInsts()">,
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AssemblerPredicate<(all_of FeatureF16BF16ToFP6BF6ConversionScaleInsts)>;
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def HasF32ToF16BF16ConversionSRInsts : Predicate<"Subtarget->hasF32ToF16BF16ConversionSRInsts()">,
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AssemblerPredicate<(all_of FeatureF32ToF16BF16ConversionSRInsts)>;
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def HasGDS : Predicate<"Subtarget->hasGDS()">;
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def HasGWS : Predicate<"Subtarget->hasGWS()">;

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h‎

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Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ class AMDGPUSubtarget {
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bool HasFP4ConversionScaleInsts = false;
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bool HasFP6BF6ConversionScaleInsts = false;
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bool HasF16BF16ToFP6BF6ConversionScaleInsts = false;
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bool HasF32ToF16BF16ConversionSRInsts = false;
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bool EnableRealTrue16Insts = false;
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bool HasBF16ConversionInsts = false;
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bool HasMadMixInsts = false;
@@ -190,6 +191,10 @@ class AMDGPUSubtarget {
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bool hasF16BF16ToFP6BF6ConversionScaleInsts() const { return HasF16BF16ToFP6BF6ConversionScaleInsts; }
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bool hasF32ToF16BF16ConversionSRInsts() const {
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return HasF32ToF16BF16ConversionSRInsts;
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}
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bool hasMadMacF32Insts() const {
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return HasMadMacF32Insts || !isGCN();
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}

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2850,6 +2850,8 @@ def VOP_V2I16_V2BF16_F32 : VOPProfile<[v2i16, v2bf16, f32, untyped]>;
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def VOP_I32_F32_F32_F32 : VOPProfile<[i32, f32, f32, f32]>;
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def VOP_I32_V2F16_F32_F32 : VOPProfile<[i32, v2f16, f32, f32]>;
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def VOP_I32_V2BF16_F32_F32: VOPProfile<[i32, v2bf16, f32, f32]>;
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def VOP_BF16_F32_I32 : VOPProfile<[bf16, f32, i32, untyped]>;
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def VOP_F16_F32_I32 : VOPProfile<[f16, f32, i32, untyped]>;
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def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
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def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1268,6 +1268,12 @@ let SubtargetPredicate = isGFX11Plus in {
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defm V_CVT_PK_U16_F32 : VOP3Inst<"v_cvt_pk_u16_f32", VOP3_Profile<VOP_V2I16_F32_F32>>;
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} // End SubtargetPredicate = isGFX11Plus
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class VOP3_CVT_SR_FP16_TiedInput_Profile<VOPProfile P> : VOP3_CVT_SCALE_F1632_FP8BF8_TiedInput_Profile<P> {
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let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0,
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Int32InputMods:$src1_modifiers, Src1RC64:$src1,
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VGPR_32:$vdst_in, op_sel0:$op_sel);
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}
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// FIXME: GlobalISel cannot distinguish f16 and bf16 and may start using bf16 patterns
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// instead of less complex f16. Disable GlobalISel for these for now.
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def bf16_fpround : PatFrag <(ops node:$src0), (fpround $src0), [{ return true; }]> {
@@ -1292,6 +1298,13 @@ let SubtargetPredicate = HasBF16ConversionInsts in {
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(V_CVT_PK_BF16_F32_e64 0, (f32 (V_CVT_F32_F64_e64 $src0_modifiers, $src0)), 0, (f32 (IMPLICIT_DEF)))>;
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}
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let SubtargetPredicate = HasF32ToF16BF16ConversionSRInsts in {
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let Constraints = "$vdst = $vdst_in", DisableEncoding = "$vdst_in" in {
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defm V_CVT_SR_F16_F32 : VOP3Inst<"v_cvt_sr_f16_f32", VOP3_CVT_SR_FP16_TiedInput_Profile<VOP_F16_F32_I32>>;
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defm V_CVT_SR_BF16_F32 : VOP3Inst<"v_cvt_sr_bf16_f32", VOP3_CVT_SR_FP16_TiedInput_Profile<VOP_BF16_F32_I32>>;
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}
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}
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let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
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defm V_MAXIMUMMINIMUM_F32 : VOP3Inst<"v_maximumminimum_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
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defm V_MINIMUMMAXIMUM_F32 : VOP3Inst<"v_minimummaximum_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
@@ -2164,6 +2177,11 @@ defm V_CVT_SCALEF32_PK32_BF6_F16 : VOP3_Real_gfx9<0x25a, "v_cvt_scalef32_pk32_b
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defm V_CVT_SCALEF32_PK32_BF6_BF16 : VOP3_Real_gfx9<0x25b, "v_cvt_scalef32_pk32_bf6_bf16">;
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}
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let OtherPredicates = [HasF32ToF16BF16ConversionSRInsts] in {
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defm V_CVT_SR_F16_F32 : VOP3OpSel_Real_gfx9 <0x2a6>;
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defm V_CVT_SR_BF16_F32: VOP3OpSel_Real_gfx9 <0x2a7>;
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}
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defm V_ASHR_PK_I8_I32 : VOP3OpSel_Real_gfx9 <0x265>;
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defm V_ASHR_PK_U8_I32 : VOP3OpSel_Real_gfx9 <0x266>;
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‎llvm/test/MC/AMDGPU/gfx950_asm_features.s‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1375,3 +1375,35 @@ v_cvt_scalef32_sr_pk_fp4_f32 v0, |v[2:3]|, v4, v5
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// NOT-GFX950: error: instruction not supported on this GPU
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// GFX950: v_cvt_scalef32_sr_pk_fp4_f32 v0, v[2:3], v4, |v5| ; encoding: [0x00,0x04,0x3e,0xd2,0x02,0x09,0x16,0x04]
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v_cvt_scalef32_sr_pk_fp4_f32 v0, v[2:3], v4, |v5|
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_sr_f16_f32 v0, v1, v2 ; encoding: [0x00,0x00,0xa6,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_sr_f16_f32 v0, v1, v2
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_sr_bf16_f32 v0, v1, v2 ; encoding: [0x00,0x00,0xa7,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_sr_bf16_f32 v0, v1, v2
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_sr_f16_f32 v0, v1, v2 op_sel:[0,0,1] ; encoding: [0x00,0x40,0xa6,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_sr_f16_f32 v0, v1, v2 op_sel:[0,0,1]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_sr_bf16_f32 v0, v1, v2 op_sel:[0,0,1] ; encoding: [0x00,0x40,0xa7,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_sr_bf16_f32 v0, v1, v2 op_sel:[0,0,1]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_sr_f16_f32 v0, -v1, v2 ; encoding: [0x00,0x00,0xa6,0xd2,0x01,0x05,0x02,0x20]
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v_cvt_sr_f16_f32 v0, -v1, v2
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_sr_f16_f32 v0, |v1|, v2 ; encoding: [0x00,0x01,0xa6,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_sr_f16_f32 v0, |v1|, v2
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_sr_bf16_f32 v0, -v1, v2 ; encoding: [0x00,0x00,0xa7,0xd2,0x01,0x05,0x02,0x20]
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v_cvt_sr_bf16_f32 v0, -v1, v2
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_sr_bf16_f32 v0, |v1|, v2 ; encoding: [0x00,0x01,0xa7,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_sr_bf16_f32 v0, |v1|, v2

‎llvm/test/MC/AMDGPU/gfx950_err.s‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -392,3 +392,9 @@ v_pk_minimum3_f16 v0, s1, s2, v3
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
394394
v_pk_maximum3_f16 v0, s1, s2, v3
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_cvt_sr_f16_f32 v1, v2, v3 clamp
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_cvt_sr_bf16_f32 v1, v2, v3 clamp

‎llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1014,3 +1014,27 @@
10141014

10151015
# GFX950: v_cvt_scalef32_sr_pk_fp4_f32 v0, v[2:3], v4, |v5| ; encoding: [0x00,0x04,0x3e,0xd2,0x02,0x09,0x16,0x04]
10161016
0x00,0x04,0x3e,0xd2,0x02,0x09,0x16,0x04
1017+
1018+
# GFX950: v_cvt_sr_f16_f32 v0, v1, v2 ; encoding: [0x00,0x00,0xa6,0xd2,0x01,0x05,0x02,0x00]
1019+
0x00,0x00,0xa6,0xd2,0x01,0x05,0x02,0x00
1020+
1021+
# GFX950: v_cvt_sr_bf16_f32 v0, v1, v2 ; encoding: [0x00,0x00,0xa7,0xd2,0x01,0x05,0x02,0x00]
1022+
0x00,0x00,0xa7,0xd2,0x01,0x05,0x02,0x00
1023+
1024+
# GFX950: v_cvt_sr_f16_f32 v0, v1, v2 op_sel:[0,0,1] ; encoding: [0x00,0x40,0xa6,0xd2,0x01,0x05,0x02,0x00]
1025+
0x00,0x40,0xa6,0xd2,0x01,0x05,0x02,0x00
1026+
1027+
# GFX950: v_cvt_sr_bf16_f32 v0, v1, v2 op_sel:[0,0,1] ; encoding: [0x00,0x40,0xa7,0xd2,0x01,0x05,0x02,0x00]
1028+
0x00,0x40,0xa7,0xd2,0x01,0x05,0x02,0x00
1029+
1030+
# GFX950: v_cvt_sr_f16_f32 v0, -v1, v2 ; encoding: [0x00,0x00,0xa6,0xd2,0x01,0x05,0x02,0x20]
1031+
0x00,0x00,0xa6,0xd2,0x01,0x05,0x02,0x20
1032+
1033+
# GFX950: v_cvt_sr_f16_f32 v0, |v1|, v2 ; encoding: [0x00,0x01,0xa6,0xd2,0x01,0x05,0x02,0x00]
1034+
0x00,0x01,0xa6,0xd2,0x01,0x05,0x02,0x00
1035+
1036+
# GFX950: v_cvt_sr_bf16_f32 v0, -v1, v2 ; encoding: [0x00,0x00,0xa7,0xd2,0x01,0x05,0x02,0x20]
1037+
0x00,0x00,0xa7,0xd2,0x01,0x05,0x02,0x20
1038+
1039+
# GFX950: v_cvt_sr_bf16_f32 v0, |v1|, v2 ; encoding: [0x00,0x01,0xa7,0xd2,0x01,0x05,0x02,0x00]
1040+
0x00,0x01,0xa7,0xd2,0x01,0x05,0x02,0x00

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