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[AArch64][NFC] Use member variable RI instead getRegisterInfo in copyPhysReg
This patch uses the RI member variable directly in the member function AArch64InstrInfo::copyPhysReg, instead of redundant calls to the public API.
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 38 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -5068,17 +5068,15 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50685068
bool RenamableSrc) const {
50695069
if (AArch64::GPR32spRegClass.contains(DestReg) &&
50705070
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
5071-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5072-
50735071
if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
50745072
// If either operand is WSP, expand to ADD #0.
50755073
if (Subtarget.hasZeroCycleRegMoveGPR64() &&
50765074
!Subtarget.hasZeroCycleRegMoveGPR32()) {
50775075
// Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
5078-
MCRegister DestRegX = TRI->getMatchingSuperReg(
5079-
DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
5080-
MCRegister SrcRegX = TRI->getMatchingSuperReg(
5081-
SrcReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
5076+
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
5077+
&AArch64::GPR64spRegClass);
5078+
MCRegister SrcRegX = RI.getMatchingSuperReg(SrcReg, AArch64::sub_32,
5079+
&AArch64::GPR64spRegClass);
50825080
// This instruction is reading and writing X registers. This may upset
50835081
// the register scavenger and machine verifier, so we need to indicate
50845082
// that we are reading an undefined value from SrcRegX, but a proper
@@ -5101,14 +5099,14 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51015099
} else if (Subtarget.hasZeroCycleRegMoveGPR64() &&
51025100
!Subtarget.hasZeroCycleRegMoveGPR32()) {
51035101
// Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
5104-
MCRegister DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
5105-
&AArch64::GPR64spRegClass);
5102+
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
5103+
&AArch64::GPR64spRegClass);
51065104
assert(DestRegX.isValid() && "Destination super-reg not valid");
51075105
MCRegister SrcRegX =
51085106
SrcReg == AArch64::WZR
51095107
? AArch64::XZR
5110-
: TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
5111-
&AArch64::GPR64spRegClass);
5108+
: RI.getMatchingSuperReg(SrcReg, AArch64::sub_32,
5109+
&AArch64::GPR64spRegClass);
51125110
assert(SrcRegX.isValid() && "Source super-reg not valid");
51135111
// This instruction is reading and writing X registers. This may upset
51145112
// the register scavenger and machine verifier, so we need to indicate
@@ -5338,11 +5336,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53385336
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
53395337
!Subtarget.hasZeroCycleRegMoveFPR64() &&
53405338
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5341-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5342-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::dsub,
5343-
&AArch64::FPR128RegClass);
5344-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::dsub,
5345-
&AArch64::FPR128RegClass);
5339+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
5340+
&AArch64::FPR128RegClass);
5341+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
5342+
&AArch64::FPR128RegClass);
53465343
// This instruction is reading and writing Q registers. This may upset
53475344
// the register scavenger and machine verifier, so we need to indicate
53485345
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5363,11 +5360,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53635360
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
53645361
!Subtarget.hasZeroCycleRegMoveFPR64() &&
53655362
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5366-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5367-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
5368-
&AArch64::FPR128RegClass);
5369-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
5370-
&AArch64::FPR128RegClass);
5363+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
5364+
&AArch64::FPR128RegClass);
5365+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
5366+
&AArch64::FPR128RegClass);
53715367
// This instruction is reading and writing Q registers. This may upset
53725368
// the register scavenger and machine verifier, so we need to indicate
53735369
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5378,11 +5374,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53785374
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
53795375
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
53805376
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5381-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5382-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
5383-
&AArch64::FPR64RegClass);
5384-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
5385-
&AArch64::FPR64RegClass);
5377+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
5378+
&AArch64::FPR64RegClass);
5379+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
5380+
&AArch64::FPR64RegClass);
53865381
// This instruction is reading and writing D registers. This may upset
53875382
// the register scavenger and machine verifier, so we need to indicate
53885383
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5402,11 +5397,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54025397
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
54035398
!Subtarget.hasZeroCycleRegMoveFPR64() &&
54045399
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5405-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5406-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
5407-
&AArch64::FPR128RegClass);
5408-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
5409-
&AArch64::FPR128RegClass);
5400+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
5401+
&AArch64::FPR128RegClass);
5402+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
5403+
&AArch64::FPR128RegClass);
54105404
// This instruction is reading and writing Q registers. This may upset
54115405
// the register scavenger and machine verifier, so we need to indicate
54125406
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5417,11 +5411,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54175411
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
54185412
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
54195413
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5420-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5421-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
5422-
&AArch64::FPR64RegClass);
5423-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
5424-
&AArch64::FPR64RegClass);
5414+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
5415+
&AArch64::FPR64RegClass);
5416+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
5417+
&AArch64::FPR64RegClass);
54255418
// This instruction is reading and writing D registers. This may upset
54265419
// the register scavenger and machine verifier, so we need to indicate
54275420
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5445,11 +5438,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54455438
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
54465439
!Subtarget.hasZeroCycleRegMoveFPR64() &&
54475440
!Subtarget.hasZeroCycleRegMoveFPR64() && Subtarget.isNeonAvailable()) {
5448-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5449-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
5450-
&AArch64::FPR128RegClass);
5451-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
5452-
&AArch64::FPR128RegClass);
5441+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
5442+
&AArch64::FPR128RegClass);
5443+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
5444+
&AArch64::FPR128RegClass);
54535445
// This instruction is reading and writing Q registers. This may upset
54545446
// the register scavenger and machine verifier, so we need to indicate
54555447
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5460,11 +5452,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54605452
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
54615453
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
54625454
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5463-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5464-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
5465-
&AArch64::FPR64RegClass);
5466-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
5467-
&AArch64::FPR64RegClass);
5455+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
5456+
&AArch64::FPR64RegClass);
5457+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
5458+
&AArch64::FPR64RegClass);
54685459
// This instruction is reading and writing D registers. This may upset
54695460
// the register scavenger and machine verifier, so we need to indicate
54705461
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5536,9 +5527,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
55365527
}
55375528

55385529
#ifndef NDEBUG
5539-
const TargetRegisterInfo &TRI = getRegisterInfo();
5540-
errs() << TRI.getRegAsmName(DestReg) << " = COPY "
5541-
<< TRI.getRegAsmName(SrcReg) << "\n";
5530+
errs() << RI.getRegAsmName(DestReg) << " = COPY " << RI.getRegAsmName(SrcReg)
5531+
<< "\n";
55425532
#endif
55435533
llvm_unreachable("unimplemented reg-to-reg copy");
55445534
}

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