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[SPIR-V] Fix ExecutionMode generation
PR #141787 added code to emit the Fragment execution model. This required emitting the OriginUpperLeft ExecutionMode. But this was done by using the same codepath used for OpEntrypoint. This has 2 issues: - the interface variables were added to both OpEntryPoint and OpExecutionMode. - the existing OpExecutionMode logic was not used. This commit fixes this, regrouping OpExecutionMode handling in one place, and fixing bad codegen issue when interface variiables are added.
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3 files changed

+17
-14
lines changed

3 files changed

+17
-14
lines changed

llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -510,6 +510,22 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
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continue;
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MCRegister FReg = MAI->getFuncReg(&F);
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assert(FReg.isValid());
513+
514+
if (Attribute Attr = F.getFnAttribute("hlsl.shader"); Attr.isValid()) {
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// SPIR-V common validation: Fragment requires OriginUpperLeft or
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// OriginLowerLeft.
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// VUID-StandaloneSpirv-OriginLowerLeft-04653: Fragment must declare
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// OriginUpperLeft.
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if (Attr.getValueAsString() == "pixel") {
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MCInst Inst;
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Inst.setOpcode(SPIRV::OpExecutionMode);
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Inst.addOperand(MCOperand::createReg(FReg));
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unsigned EM =
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static_cast<unsigned>(SPIRV::ExecutionMode::OriginUpperLeft);
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Inst.addOperand(MCOperand::createImm(EM));
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outputMCInst(Inst);
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}
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}
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if (MDNode *Node = F.getMetadata("reqd_work_group_size"))
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outputExecutionModeFromMDNode(FReg, Node, SPIRV::ExecutionMode::LocalSize,
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3, 1);

llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

Lines changed: 1 addition & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -475,21 +475,10 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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// environment if we need to.
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const SPIRVSubtarget *ST =
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static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
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SPIRV::ExecutionModel::ExecutionModel ExecutionModel =
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getExecutionModel(*ST, F);
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint)
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.addImm(static_cast<uint32_t>(ExecutionModel))
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.addImm(static_cast<uint32_t>(getExecutionModel(*ST, F)))
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.addUse(FuncVReg);
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addStringImm(F.getName(), MIB);
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if (ExecutionModel == SPIRV::ExecutionModel::Fragment) {
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// SPIR-V common validation: Fragment requires OriginUpperLeft or
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// OriginLowerLeft VUID-StandaloneSpirv-OriginLowerLeft-04653: Fragment
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// must declare OriginUpperLeft.
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MIRBuilder.buildInstr(SPIRV::OpExecutionMode)
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.addUse(FuncVReg)
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.addImm(static_cast<uint32_t>(SPIRV::ExecutionMode::OriginUpperLeft));
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}
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} else if (F.getLinkage() != GlobalValue::InternalLinkage &&
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F.getLinkage() != GlobalValue::PrivateLinkage) {
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SPIRV::LinkageType::LinkageType LnkTy =

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -595,8 +595,6 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
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collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames, IS);
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} else if (OpCode == SPIRV::OpEntryPoint) {
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collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS);
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} else if (OpCode == SPIRV::OpExecutionMode) {
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collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS);
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} else if (TII->isAliasingInstr(MI)) {
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collectOtherInstr(MI, MAI, SPIRV::MB_AliasingInsts, IS);
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} else if (TII->isDecorationInstr(MI)) {

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