TZCNT in 1 uop

NexusXe · NexusXe · commit 3555807bcc1b · 2025-10-01T14:15:59.000-05:00
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver4.td b/llvm/lib/Target/X86/X86ScheduleZnver4.td
@@ -726,12 +726,12 @@ def Zn4WriteLZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
 }
 def : InstRW<[Zn4WriteLZCNT16rr], (instrs LZCNT16rr)>;
 
-defm : Zn4WriteResIntPair<WriteTZCNT, [Zn4ALU12], 2, [1], 2>; // Trailing zero count.
+defm : Zn4WriteResIntPair<WriteTZCNT, [Zn4ALU12], 1, [1], 1>; // Trailing zero count.
 
 def Zn4WriteTZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
-  let Latency = 2;
-  let ReleaseAtCycles = [4];
-  let NumMicroOps = 2;
+  let Latency = 1;
+  let ReleaseAtCycles = [1];
+  let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteTZCNT16rr], (instrs TZCNT16rr)>;
 

Original file line number	Diff line number	Diff line change
`@@ -726,12 +726,12 @@ def Zn4WriteLZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {`
`726`	`726`	`}`
`727`	`727`	`def : InstRW<[Zn4WriteLZCNT16rr], (instrs LZCNT16rr)>;`
`728`	`728`
`729`		`-defm : Zn4WriteResIntPair<WriteTZCNT, [Zn4ALU12], 2, [1], 2>; // Trailing zero count.`
	`729`	`+defm : Zn4WriteResIntPair<WriteTZCNT, [Zn4ALU12], 1, [1], 1>; // Trailing zero count.`
`730`	`730`
`731`	`731`	`def Zn4WriteTZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {`
`732`		`- let Latency = 2;`
`733`		`- let ReleaseAtCycles = [4];`
`734`		`- let NumMicroOps = 2;`
	`732`	`+ let Latency = 1;`
	`733`	`+ let ReleaseAtCycles = [1];`
	`734`	`+ let NumMicroOps = 1;`
`735`	`735`	`}`
`736`	`736`	`def : InstRW<[Zn4WriteTZCNT16rr], (instrs TZCNT16rr)>;`
`737`	`737`