|
33 | 33 | #include "llvm/Support/Casting.h" |
34 | 34 | #include "llvm/Support/ErrorHandling.h" |
35 | 35 | #include "llvm/Support/SMLoc.h" |
| 36 | +#include "llvm/TargetParser/SubtargetFeature.h" |
36 | 37 | #include <algorithm> |
37 | 38 | #include <cassert> |
38 | 39 | #include <cstddef> |
@@ -410,6 +411,18 @@ class SystemZAsmParser : public MCTargetAsmParser { |
410 | 411 |
|
411 | 412 | private: |
412 | 413 | MCAsmParser &Parser; |
| 414 | + |
| 415 | + // A vector to contain the stack of machine specs created by `.machine push`. |
| 416 | + SmallVector<StringRef> MachineStack; |
| 417 | + // Specifies the current CPU. It is initialized to "default", which represents |
| 418 | + // the feature bit set in use before any `.machine` directive is issued. |
| 419 | + StringRef CurrentCPU = "default"; |
| 420 | + // The feature bits associated with the "default" cpu. Derived from the |
| 421 | + // SubtargetInfo handed to the constructor of the AsmParser. This is |
| 422 | + // used to recreate the feature bits if the "default" cpu is saved by a |
| 423 | + // `.machine push` and then restored by a `.machine pop`. |
| 424 | + const FeatureBitset &DefaultBits; |
| 425 | + |
413 | 426 | enum RegisterGroup { |
414 | 427 | RegGR, |
415 | 428 | RegFP, |
@@ -494,16 +507,16 @@ class SystemZAsmParser : public MCTargetAsmParser { |
494 | 507 |
|
495 | 508 | public: |
496 | 509 | SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, |
497 | | - const MCInstrInfo &MII, |
498 | | - const MCTargetOptions &Options) |
499 | | - : MCTargetAsmParser(Options, sti, MII), Parser(parser) { |
| 510 | + const MCInstrInfo &MII, const MCTargetOptions &Options) |
| 511 | + : MCTargetAsmParser(Options, sti, MII), Parser(parser), |
| 512 | + DefaultBits(sti.getFeatureBits()) { |
500 | 513 | MCAsmParserExtension::Initialize(Parser); |
501 | 514 |
|
502 | 515 | // Alias the .word directive to .short. |
503 | 516 | parser.addAliasForDirective(".word", ".short"); |
504 | 517 |
|
505 | 518 | // Initialize the set of available features. |
506 | | - setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); |
| 519 | + setAvailableFeatures(ComputeAvailableFeatures(DefaultBits)); |
507 | 520 | } |
508 | 521 |
|
509 | 522 | // Override MCTargetAsmParser. |
@@ -1382,17 +1395,39 @@ bool SystemZAsmParser::parseDirectiveMachine(SMLoc L) { |
1382 | 1395 | Parser.getTok().isNot(AsmToken::String)) |
1383 | 1396 | return TokError("unexpected token in '.machine' directive"); |
1384 | 1397 |
|
1385 | | - StringRef CPU = Parser.getTok().getIdentifier(); |
| 1398 | + StringRef Id = Parser.getTok().getIdentifier(); |
| 1399 | + |
| 1400 | + // Parse push and pop directives first |
| 1401 | + StringRef CPU = ""; |
| 1402 | + if (Id == "push") { |
| 1403 | + if (CurrentCPU.empty()) |
| 1404 | + llvm_unreachable(".machine push without a cpu to save"); |
| 1405 | + MachineStack.push_back(CurrentCPU); |
| 1406 | + } else if (Id == "pop") { |
| 1407 | + if (MachineStack.empty()) |
| 1408 | + return TokError("pop without corresponding push in '.machine' directive"); |
| 1409 | + CPU = MachineStack.back(); |
| 1410 | + MachineStack.pop_back(); |
| 1411 | + } else { |
| 1412 | + CPU = Id; |
| 1413 | + } |
| 1414 | + |
1386 | 1415 | Parser.Lex(); |
1387 | 1416 | if (parseEOL()) |
1388 | 1417 | return true; |
1389 | 1418 |
|
1390 | | - MCSubtargetInfo &STI = copySTI(); |
1391 | | - STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, ""); |
1392 | | - setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); |
1393 | | - |
1394 | | - getTargetStreamer().emitMachine(CPU); |
| 1419 | + // check if we need to change cpu |
| 1420 | + if (CPU == "default") { |
| 1421 | + setAvailableFeatures(DefaultBits); |
| 1422 | + CurrentCPU = "default"; |
| 1423 | + } else if (!CPU.empty()) { |
| 1424 | + MCSubtargetInfo &STI = copySTI(); |
| 1425 | + STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, ""); |
| 1426 | + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); |
| 1427 | + CurrentCPU = CPU; |
1395 | 1428 |
|
| 1429 | + getTargetStreamer().emitMachine(CPU); |
| 1430 | + } |
1396 | 1431 | return false; |
1397 | 1432 | } |
1398 | 1433 |
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