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Created using spr 1.3.5

Author: koachan

llvm/lib/Target/Sparc/SparcInstrFormats.td

@@ -205,15 +205,15 @@ class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
 class F3_3_siam<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
            string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
    : F3<outs, ins, asmstr, pattern, itin> {
-  bits<3> uimm3;
+  bits<3> mode;
 
   let op         = opVal;
   let op3        = op3val;
   let rd         = 0;
   let rs1        = 0;
   let Inst{13-5} = opfval;   // fp opcode
   let Inst{4-3}  = 0;
-  let Inst{2-0}  = uimm3;
+  let Inst{2-0}  = mode;
 }
 
 // Shift by register rs2.

llvm/lib/Target/Sparc/SparcInstrVIS.td

@@ -167,7 +167,7 @@ def BSHUFFLE  : VISInst<0b001001100, "bshuffle">;
 
 let rd = 0, rs1 = 0 in
 def SIAM      : F3_3_siam<0b10, 0b110110, 0b010000001, (outs),
-                (ins i32imm:$uimm3), "siam $uimm3", []>;
+                (ins i32imm:$mode), "siam $mode", []>;
 
 def EDGE8N    : VISInst<0b000000001,  "edge8n",   I64Regs>;
 def EDGE8LN   : VISInst<0b000000011,  "edge8ln",  I64Regs>;