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Pravin Jagtap
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[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. (#109685)
Both SGPR->VGPR and VGPR->AGPR spilling code give a fixup to the spill frame indices referred in debug instructions so that they can be entirely removed. The stack argument is present at 0th index in DBG_VALUE and at 2nd index for DBG_VALUE_LIST. Fixes: SWDEV-484156
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4 files changed

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lines changed

‎llvm/lib/Target/AMDGPU/SIFrameLowering.cpp‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1418,10 +1418,15 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
14181418
// the debug value instructions. We should instead, update it with the
14191419
// correct register value. But not sure the register value alone is
14201420
for (MachineInstr &MI : MBB) {
1421-
if (MI.isDebugValue() && MI.getOperand(0).isFI() &&
1422-
!MFI.isFixedObjectIndex(MI.getOperand(0).getIndex()) &&
1423-
SpillFIs[MI.getOperand(0).getIndex()]) {
1424-
MI.getOperand(0).ChangeToRegister(Register(), false /*isDef*/);
1421+
if (MI.isDebugValue()) {
1422+
uint32_t StackOperandIdx = MI.isDebugValueList() ? 2 : 0;
1423+
if (MI.getOperand(StackOperandIdx).isFI() &&
1424+
!MFI.isFixedObjectIndex(
1425+
MI.getOperand(StackOperandIdx).getIndex()) &&
1426+
SpillFIs[MI.getOperand(StackOperandIdx).getIndex()]) {
1427+
MI.getOperand(StackOperandIdx)
1428+
.ChangeToRegister(Register(), false /*isDef*/);
1429+
}
14251430
}
14261431
}
14271432
}

‎llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -418,10 +418,15 @@ bool SILowerSGPRSpills::run(MachineFunction &MF) {
418418
// correct register value. But not sure the register value alone is
419419
// adequate to lower the DIExpression. It should be worked out later.
420420
for (MachineInstr &MI : MBB) {
421-
if (MI.isDebugValue() && MI.getOperand(0).isFI() &&
422-
!MFI.isFixedObjectIndex(MI.getOperand(0).getIndex()) &&
423-
SpillFIs[MI.getOperand(0).getIndex()]) {
424-
MI.getOperand(0).ChangeToRegister(Register(), false /*isDef*/);
421+
if (MI.isDebugValue()) {
422+
uint32_t StackOperandIdx = MI.isDebugValueList() ? 2 : 0;
423+
if (MI.getOperand(StackOperandIdx).isFI() &&
424+
!MFI.isFixedObjectIndex(
425+
MI.getOperand(StackOperandIdx).getIndex()) &&
426+
SpillFIs[MI.getOperand(StackOperandIdx).getIndex()]) {
427+
MI.getOperand(StackOperandIdx)
428+
.ChangeToRegister(Register(), false /*isDef*/);
429+
}
425430
}
426431
}
427432
}

‎llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir‎

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
2+
3+
--- |
4+
define amdgpu_kernel void @test() { ret void }
5+
6+
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4, producer: "llvm", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, retainedTypes: !4)
7+
!1 = !DILocalVariable(name: "a", scope: !2, file: !4, line: 126, type: !6)
8+
!2 = distinct !DISubprogram(name: "test", scope: !4, file: !4, line: 1, type: !3, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !5)
9+
!3 = !DISubroutineType(types: !4)
10+
!4 = !DIFile(filename: "dummy", directory: "/")
11+
!5 = !{!1}
12+
!6 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 64, align: 32)
13+
!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
14+
!8 = !DIExpression()
15+
!9 = !DILocation(line: 10, column: 9, scope: !2)
16+
17+
...
18+
---
19+
name: test
20+
tracksRegLiveness: true
21+
frameInfo:
22+
maxAlignment: 4
23+
fixedStack:
24+
- { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default }
25+
stack:
26+
- { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
27+
machineFunctionInfo:
28+
maxKernArgAlign: 4
29+
isEntryFunction: true
30+
waveLimiter: true
31+
scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
32+
stackPtrOffsetReg: '$sgpr32'
33+
frameOffsetReg: '$sgpr33'
34+
hasSpilledSGPRs: true
35+
argumentInfo:
36+
privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
37+
dispatchPtr: { reg: '$sgpr4_sgpr5' }
38+
kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
39+
workGroupIDX: { reg: '$sgpr8' }
40+
privateSegmentWaveByteOffset: { reg: '$sgpr9' }
41+
body: |
42+
; CHECK-LABEL: name: test
43+
; CHECK: bb.0:
44+
; CHECK: DBG_VALUE_LIST <{{.*}}>, !DIExpression(), $noreg, 0, debug-location !DILocation(line: 10, column: 9, scope: <{{.*}}>)
45+
46+
bb.0:
47+
renamable $sgpr10 = IMPLICIT_DEF
48+
SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
49+
DBG_VALUE_LIST !1, !8, %stack.0, 0, debug-location !9
50+
51+
bb.1:
52+
renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
53+
S_ENDPGM 0

‎llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=true -run-pass=prologepilog -o - %s | FileCheck %s
2+
3+
--- |
4+
define amdgpu_kernel void @test() { ret void }
5+
6+
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4, producer: "llvm", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, retainedTypes: !4)
7+
!1 = !DILocalVariable(name: "a", scope: !2, file: !4, line: 126, type: !6)
8+
!2 = distinct !DISubprogram(name: "test", scope: !4, file: !4, line: 1, type: !3, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !5)
9+
!3 = !DISubroutineType(types: !4)
10+
!4 = !DIFile(filename: "dummy", directory: "/")
11+
!5 = !{!1}
12+
!6 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 64, align: 32)
13+
!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
14+
!8 = !DIExpression()
15+
!9 = !DILocation(line: 10, column: 9, scope: !2)
16+
17+
...
18+
---
19+
name: test
20+
tracksRegLiveness: true
21+
frameInfo:
22+
maxAlignment: 4
23+
fixedStack:
24+
- { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default }
25+
stack:
26+
- { id: 0, type: spill-slot, size: 4, alignment: 4 }
27+
machineFunctionInfo:
28+
maxKernArgAlign: 4
29+
isEntryFunction: true
30+
waveLimiter: true
31+
scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
32+
stackPtrOffsetReg: '$sgpr32'
33+
frameOffsetReg: '$sgpr33'
34+
hasSpilledVGPRs: true
35+
argumentInfo:
36+
privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
37+
dispatchPtr: { reg: '$sgpr4_sgpr5' }
38+
kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
39+
workGroupIDX: { reg: '$sgpr8' }
40+
privateSegmentWaveByteOffset: { reg: '$sgpr9' }
41+
body: |
42+
; CHECK-LABEL: name: test
43+
; CHECK: bb.0:
44+
; CHECK: DBG_VALUE_LIST <{{.*}}>, !DIExpression(), $noreg, 0, debug-location !DILocation(line: 10, column: 9, scope: <{{.*}}>)
45+
bb.0:
46+
$vgpr2 = IMPLICIT_DEF
47+
SI_SPILL_V32_SAVE $vgpr2, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, align 4, addrspace 5)
48+
DBG_VALUE_LIST !1, !8, %stack.0, 0, debug-location !9
49+
50+
bb.1:
51+
renamable $vgpr2 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, align 4, addrspace 5)
52+
S_ENDPGM 0

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