Delete stale code

Change-Id: I1ebeebd405e773e494ad7242f9a0017f1b5f6013

Author: jrbyrnes

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -941,12 +941,10 @@ void GCNScheduleDAGMILive::finalizeSchedule() {
   Pressure.resize(Regions.size());
   RegionsWithHighRP.resize(Regions.size());
   RegionsWithExcessRP.resize(Regions.size());
-  RegionsWithExcessVGPRRP.resize(Regions.size());
   RegionsWithMinOcc.resize(Regions.size());
   RegionsWithIGLPInstrs.resize(Regions.size());
   RegionsWithHighRP.reset();
   RegionsWithExcessRP.reset();
-  RegionsWithExcessVGPRRP.reset();
   RegionsWithMinOcc.reset();
   RegionsWithIGLPInstrs.reset();
 
@@ -1341,9 +1339,6 @@ void GCNSchedStage::checkScheduling() {
   unsigned MaxArchVGPRs = std::min(MaxVGPRs, ST.getAddressableNumArchVGPRs());
   unsigned MaxSGPRs = ST.getMaxNumSGPRs(MF);
 
-  if (PressureAfter.getArchVGPRNum() > ST.getAddressableNumArchVGPRs())
-    DAG.RegionsWithExcessVGPRRP[RegionIdx] = true;
-
   if (PressureAfter.getVGPRNum(ST.hasGFX90AInsts()) > MaxVGPRs ||
       PressureAfter.getArchVGPRNum() > MaxArchVGPRs ||
       PressureAfter.getAGPRNum() > MaxArchVGPRs ||

llvm/lib/Target/AMDGPU/GCNSchedStrategy.h

@@ -250,9 +250,6 @@ class GCNScheduleDAGMILive final : public ScheduleDAGMILive {
   // limit. Register pressure in these regions usually will result in spilling.
   BitVector RegionsWithExcessRP;
 
-  // Regions that have VGPR RP which exceed the addressable limit.
-  BitVector RegionsWithExcessVGPRRP;
-
   // Regions that has the same occupancy as the latest MinOccupancy
   BitVector RegionsWithMinOcc;