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[AArch64][PowerPC]: Reverting some updates
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-81
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4 files changed

+14
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‎llvm/test/CodeGen/AArch64/eon.ll‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,13 +36,22 @@ entry:
3636

3737
; Check that eon is generated if the xor is a disjoint or.
3838
define i64 @disjoint_or(i64 %a, i64 %b) {
39+
; CHECK-LABEL: disjoint_or:
40+
; CHECK: // %bb.0:
41+
; CHECK-NEXT: eon x0, x0, x1
42+
; CHECK-NEXT: ret
3943
%or = or disjoint i64 %a, %b
4044
%eon = xor i64 %or, -1
4145
ret i64 %eon
4246
}
4347

4448
; Check that eon is *not* generated if the or is not disjoint.
4549
define i64 @normal_or(i64 %a, i64 %b) {
50+
; CHECK-LABEL: normal_or:
51+
; CHECK: // %bb.0:
52+
; CHECK-NEXT: orr x8, x0, x1
53+
; CHECK-NEXT: mvn x0, x8
54+
; CHECK-NEXT: ret
4655
%or = or i64 %a, %b
4756
%not = xor i64 %or, -1
4857
ret i64 %not

‎llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
21
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
32
; RUN: grep eqv | count 3
43
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \

‎llvm/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll‎

Lines changed: 5 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,29 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
21
; Check the miscellaneous logical vector operations added in P8
3-
;
2+
;
43
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
54
; Test x eqv y
65
define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
7-
; CHECK-LABEL: test_veqv:
8-
; CHECK: # %bb.0:
9-
; CHECK-NEXT: veqv 2, 2, 3
10-
; CHECK-NEXT: blr
116
%tmp = xor <4 x i32> %x, %y
127
%ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
138
ret <4 x i32> %ret_val
9+
; CHECK: veqv 2, 2, 3
1410
}
1511

1612
; Test x vnand y
1713
define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
18-
; CHECK-LABEL: test_vnand:
19-
; CHECK: # %bb.0:
20-
; CHECK-NEXT: vnand 2, 2, 3
21-
; CHECK-NEXT: blr
2214
%tmp = and <4 x i32> %x, %y
2315
%ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
2416
ret <4 x i32> %ret_val
17+
; CHECK: vnand 2, 2, 3
2518
}
2619

2720
; Test x vorc y and variants
2821
define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
29-
; CHECK-LABEL: test_vorc:
30-
; CHECK: # %bb.0:
31-
; CHECK-NEXT: vorc 3, 2, 3
32-
; CHECK-NEXT: vorc 2, 2, 3
33-
; CHECK-NEXT: blr
3422
%tmp1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
3523
%tmp2 = or <4 x i32> %x, %tmp1
24+
; CHECK: vorc 3, 2, 3
3625
%tmp3 = xor <4 x i32> %tmp2, <i32 -1, i32 -1, i32 -1, i32 -1>
3726
%tmp4 = or <4 x i32> %tmp3, %x
27+
; CHECK: vorc 2, 2, 3
3828
ret <4 x i32> %tmp4
3929
}

‎llvm/test/CodeGen/PowerPC/xxeval-and-nand.ll‎

Lines changed: 0 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
21
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
32
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
43

@@ -7,10 +6,6 @@
76
; CHECK: xxlandc v2, v2, v3
87
; CHECK-NEXT: blr
98
define dso_local <4 x i32> @and_not(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
10-
; CHECK-LABEL: and_not:
11-
; CHECK: # %bb.0: # %entry
12-
; CHECK-NEXT: xxlandc v2, v2, v3
13-
; CHECK-NEXT: blr
149
entry:
1510
%neg = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
1611
%and = and <4 x i32> %neg, %A
@@ -22,10 +17,6 @@ entry:
2217
; CHECK: xxeval v2, v3, v2, v4, 1
2318
; CHECK-NEXT: blr
2419
define dso_local <16 x i8> @and_and8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) local_unnamed_addr #0 {
25-
; CHECK-LABEL: and_and8:
26-
; CHECK: # %bb.0: # %entry
27-
; CHECK-NEXT: xxeval v2, v3, v2, v4, 1
28-
; CHECK-NEXT: blr
2920
entry:
3021
%and = and <16 x i8> %B, %A
3122
%and1 = and <16 x i8> %and, %C
@@ -37,10 +28,6 @@ entry:
3728
; CHECK: xxeval v2, v3, v2, v4, 1
3829
; CHECK-NEXT: blr
3930
define dso_local <8 x i16> @and_and16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) local_unnamed_addr #0 {
40-
; CHECK-LABEL: and_and16:
41-
; CHECK: # %bb.0: # %entry
42-
; CHECK-NEXT: xxeval v2, v3, v2, v4, 1
43-
; CHECK-NEXT: blr
4431
entry:
4532
%and = and <8 x i16> %B, %A
4633
%and1 = and <8 x i16> %and, %C
@@ -52,10 +39,6 @@ entry:
5239
; CHECK: xxeval v2, v3, v2, v4, 1
5340
; CHECK-NEXT: blr
5441
define dso_local <4 x i32> @and_and32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
55-
; CHECK-LABEL: and_and32:
56-
; CHECK: # %bb.0: # %entry
57-
; CHECK-NEXT: xxeval v2, v3, v2, v4, 1
58-
; CHECK-NEXT: blr
5942
entry:
6043
%and = and <4 x i32> %B, %A
6144
%and1 = and <4 x i32> %and, %C
@@ -67,10 +50,6 @@ entry:
6750
; CHECK: xxeval v2, v3, v2, v4, 1
6851
; CHECK-NEXT: blr
6952
define dso_local <2 x i64> @and_and64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
70-
; CHECK-LABEL: and_and64:
71-
; CHECK: # %bb.0: # %entry
72-
; CHECK-NEXT: xxeval v2, v3, v2, v4, 1
73-
; CHECK-NEXT: blr
7453
entry:
7554
%and = and <2 x i64> %B, %A
7655
%and1 = and <2 x i64> %and, %C
@@ -82,10 +61,6 @@ entry:
8261
; CHECK: xxeval v2, v2, v4, v3, 14
8362
; CHECK-NEXT: blr
8463
define dso_local <4 x i32> @and_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
85-
; CHECK-LABEL: and_nand:
86-
; CHECK: # %bb.0: # %entry
87-
; CHECK-NEXT: xxeval v2, v2, v4, v3, 14
88-
; CHECK-NEXT: blr
8964
entry:
9065
%and = and <4 x i32> %C, %B
9166
%neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -98,10 +73,6 @@ entry:
9873
; CHECK: xxeval v2, v2, v4, v3, 7
9974
; CHECK-NEXT: blr
10075
define dso_local <4 x i32> @and_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
101-
; CHECK-LABEL: and_or:
102-
; CHECK: # %bb.0: # %entry
103-
; CHECK-NEXT: xxeval v2, v2, v4, v3, 7
104-
; CHECK-NEXT: blr
10576
entry:
10677
%or = or <4 x i32> %C, %B
10778
%and = and <4 x i32> %or, %A
@@ -113,10 +84,6 @@ entry:
11384
; CHECK: xxeval v2, v2, v4, v3, 8
11485
; CHECK-NEXT: blr
11586
define dso_local <4 x i32> @and_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
116-
; CHECK-LABEL: and_nor:
117-
; CHECK: # %bb.0: # %entry
118-
; CHECK-NEXT: xxeval v2, v2, v4, v3, 8
119-
; CHECK-NEXT: blr
12087
entry:
12188
%or = or <4 x i32> %C, %B
12289
%neg = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -129,10 +96,6 @@ entry:
12996
; CHECK: xxeval v2, v2, v4, v3, 6
13097
; CHECK-NEXT: blr
13198
define dso_local <4 x i32> @and_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
132-
; CHECK-LABEL: and_xor:
133-
; CHECK: # %bb.0: # %entry
134-
; CHECK-NEXT: xxeval v2, v2, v4, v3, 6
135-
; CHECK-NEXT: blr
13699
entry:
137100
%xor = xor <4 x i32> %C, %B
138101
%and = and <4 x i32> %xor, %A
@@ -144,10 +107,6 @@ entry:
144107
; CHECK: xxeval v2, v2, v3, v4, 9
145108
; CHECK-NEXT: blr
146109
define dso_local <4 x i32> @and_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
147-
; CHECK-LABEL: and_eqv:
148-
; CHECK: # %bb.0: # %entry
149-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 9
150-
; CHECK-NEXT: blr
151110
entry:
152111
%xor = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
153112
%neg = xor <4 x i32> %xor, %C
@@ -160,10 +119,6 @@ entry:
160119
; CHECK: xxeval v2, v2, v4, v3, 241
161120
; CHECK-NEXT: blr
162121
define dso_local <4 x i32> @nand_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
163-
; CHECK-LABEL: nand_nand:
164-
; CHECK: # %bb.0: # %entry
165-
; CHECK-NEXT: xxeval v2, v2, v4, v3, 241
166-
; CHECK-NEXT: blr
167122
entry:
168123
%and = and <4 x i32> %C, %B
169124
%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -176,10 +131,6 @@ entry:
176131
; CHECK: xxeval v2, v3, v2, v4, 254
177132
; CHECK-NEXT: blr
178133
define dso_local <4 x i32> @nand_and(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
179-
; CHECK-LABEL: nand_and:
180-
; CHECK: # %bb.0: # %entry
181-
; CHECK-NEXT: xxeval v2, v3, v2, v4, 254
182-
; CHECK-NEXT: blr
183134
entry:
184135
%and = and <4 x i32> %B, %A
185136
%and1 = and <4 x i32> %and, %C
@@ -192,10 +143,6 @@ entry:
192143
; CHECK: xxeval v2, v2, v4, v3, 249
193144
; CHECK-NEXT: blr
194145
define dso_local <4 x i32> @nand_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
195-
; CHECK-LABEL: nand_xor:
196-
; CHECK: # %bb.0: # %entry
197-
; CHECK-NEXT: xxeval v2, v2, v4, v3, 249
198-
; CHECK-NEXT: blr
199146
entry:
200147
%xor = xor <4 x i32> %C, %B
201148
%and = and <4 x i32> %xor, %A
@@ -208,10 +155,6 @@ entry:
208155
; CHECK: xxeval v2, v2, v4, v3, 246
209156
; CHECK-NEXT: blr
210157
define dso_local <4 x i32> @nand_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
211-
; CHECK-LABEL: nand_eqv:
212-
; CHECK: # %bb.0: # %entry
213-
; CHECK-NEXT: xxeval v2, v2, v4, v3, 246
214-
; CHECK-NEXT: blr
215158
entry:
216159
%xor = xor <4 x i32> %C, %B
217160
%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -224,10 +167,6 @@ entry:
224167
; CHECK: xxeval v2, v2, v4, v3, 248
225168
; CHECK-NEXT: blr
226169
define dso_local <4 x i32> @nand_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
227-
; CHECK-LABEL: nand_or:
228-
; CHECK: # %bb.0: # %entry
229-
; CHECK-NEXT: xxeval v2, v2, v4, v3, 248
230-
; CHECK-NEXT: blr
231170
entry:
232171
%or = or <4 x i32> %C, %B
233172
%and = and <4 x i32> %or, %A
@@ -240,10 +179,6 @@ entry:
240179
; CHECK: xxeval v2, v2, v3, v4, 247
241180
; CHECK-NEXT: blr
242181
define dso_local <4 x i32> @nand_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
243-
; CHECK-LABEL: nand_nor:
244-
; CHECK: # %bb.0: # %entry
245-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 247
246-
; CHECK-NEXT: blr
247182
entry:
248183
%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
249184
%or = or <4 x i32> %A.not, %B

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