chore: Fix formatting

Author: ahmednoursphinx

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -365,17 +365,17 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
 
     assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
     NumParts = NumRegs; // Silence a compiler warning.
-    
+
     // Check if the register type matches the part type
     if (RegisterVT != PartVT) {
-      diagnosePossiblyInvalidConstraint(
-          *DAG.getContext(), V,
-          "register type (" + EVT(RegisterVT).getEVTString() +
-              ") doesn't match operand type (" + EVT(PartVT).getEVTString() +
-              ")");
+      diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
+                                        "register type (" +
+                                            EVT(RegisterVT).getEVTString() +
+                                            ") doesn't match operand type (" +
+                                            EVT(PartVT).getEVTString() + ")");
       return DAG.getUNDEF(ValueVT);
     }
-    
+
     assert(RegisterVT.getSizeInBits() ==
            Parts[0].getSimpleValueType().getSizeInBits() &&
            "Part type sizes don't match!");

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -61826,7 +61826,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     case 'y':   // MMX_REGS if MMX allowed.
       if (!Subtarget.hasMMX()) break;
       // MMX registers are 64-bit only
-      if (VT.getSizeInBits() != 64) break;
+      if (VT.getSizeInBits() != 64)
+        break;
       return std::make_pair(0U, &X86::VR64RegClass);
     case 'v':
     case 'x':   // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed