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1 parent 95ae663 commit 36d72a1Copy full SHA for 36d72a1
mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
@@ -2185,7 +2185,7 @@ def Vector_CompressStoreOp :
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correspond to those of the `llvm.masked.compressstore`
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[intrinsic](https://llvm.org/docs/LangRef.html#llvm-masked-compressstore-intrinsics).
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- Note that the index increment is done conditionally.
+ Note, at the moment this Op is only available for fixed-width vectors.
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Examples:
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