clang-format

Author: akshayrdeodhar

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -2325,13 +2325,13 @@ class LLVM_ABI TargetLoweringBase {
   ///   standard ABI uses a fence before a seq_cst load instead of after a
   ///   seq_cst store).
   /// @{
-  virtual Instruction *
-  emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
-                   AtomicOrdering Ord) const;
+  virtual Instruction *emitLeadingFence(IRBuilderBase &Builder,
+                                        Instruction *Inst,
+                                        AtomicOrdering Ord) const;
 
-  virtual Instruction *
-  emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
-                    AtomicOrdering Ord) const;
+  virtual Instruction *emitTrailingFence(IRBuilderBase &Builder,
+                                         Instruction *Inst,
+                                         AtomicOrdering Ord) const;
   /// @}
 
   // Emits code that executes when the comparison result in the ll/sc

llvm/lib/Target/ARM/ARMISelLowering.h

@@ -674,10 +674,10 @@ class VectorType;
     void
     emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
 
-    Instruction *emitLeadingFence(
-        IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override;
-    Instruction *emitTrailingFence(
-        IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override;
+    Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
+                                  AtomicOrdering Ord) const override;
+    Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
+                                   AtomicOrdering Ord) const override;
 
     unsigned getMaxSupportedInterleaveFactor() const override;
 

llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp

@@ -269,7 +269,7 @@ void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
 }
 
 void NVPTXInstPrinter::printAtomicCode(const MCInst *MI, int OpNum,
-                                     raw_ostream &O, StringRef Modifier) {
+                                       raw_ostream &O, StringRef Modifier) {
   const MCOperand &MO = MI->getOperand(OpNum);
   int Imm = (int)MO.getImm();
   if (Modifier == "sem") {
@@ -321,9 +321,9 @@ void NVPTXInstPrinter::printAtomicCode(const MCInst *MI, int OpNum,
       O << ".gpu";
       return;
     }
-    report_fatal_error(
-        formatv("NVPTX AtomicCode Printer does not support \"{}\" scope modifier.",
-                ScopeToString(S)));
+    report_fatal_error(formatv(
+        "NVPTX AtomicCode Printer does not support \"{}\" scope modifier.",
+        ScopeToString(S)));
   } else if (Modifier == "addsp") {
     auto A = NVPTX::AddressSpace(Imm);
     switch (A) {

llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h

@@ -41,7 +41,7 @@ class NVPTXInstPrinter : public MCInstPrinter {
   void printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
                     StringRef Modifier = {});
   void printAtomicCode(const MCInst *MI, int OpNum, raw_ostream &O,
-                     StringRef Modifier = {});
+                       StringRef Modifier = {});
   void printMmaCode(const MCInst *MI, int OpNum, raw_ostream &O,
                     StringRef Modifier = {});
   void printMemOperand(const MCInst *MI, int OpNum, raw_ostream &O,

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

@@ -304,7 +304,6 @@ void NVPTXDAGToDAGISel::SelectTcgen05Ld(SDNode *N, bool hasOffset) {
   }
 }
 
-
 bool NVPTXDAGToDAGISel::tryIntrinsicChain(SDNode *N) {
   unsigned IID = N->getConstantOperandVal(1);
   switch (IID) {
@@ -525,19 +524,19 @@ unsigned int NVPTXDAGToDAGISel::getMemOrder(const MemSDNode *N) const {
     return NVPTX::Ordering::NotAtomic;
   auto Ordering = N->getMergedOrdering();
   switch (Ordering) {
-    case AtomicOrdering::NotAtomic:
-    case AtomicOrdering::Unordered:
-      return NVPTX::Ordering::NotAtomic;
-    case AtomicOrdering::Monotonic:
-      return NVPTX::Ordering::Relaxed;
-    case AtomicOrdering::Acquire:
-      return NVPTX::Ordering::Acquire;
-    case AtomicOrdering::Release:
-      return NVPTX::Ordering::Release;
-    case AtomicOrdering::AcquireRelease:
-      return NVPTX::Ordering::AcquireRelease;
-    case AtomicOrdering::SequentiallyConsistent:
-      return NVPTX::Ordering::SequentiallyConsistent;
+  case AtomicOrdering::NotAtomic:
+  case AtomicOrdering::Unordered:
+    return NVPTX::Ordering::NotAtomic;
+  case AtomicOrdering::Monotonic:
+    return NVPTX::Ordering::Relaxed;
+  case AtomicOrdering::Acquire:
+    return NVPTX::Ordering::Acquire;
+  case AtomicOrdering::Release:
+    return NVPTX::Ordering::Release;
+  case AtomicOrdering::AcquireRelease:
+    return NVPTX::Ordering::AcquireRelease;
+  case AtomicOrdering::SequentiallyConsistent:
+    return NVPTX::Ordering::SequentiallyConsistent;
   }
 }
 

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -232,12 +232,10 @@ class RISCVTargetLowering : public TargetLowering {
   // than this hook due to limitations in the interface here.
   bool shouldInsertFencesForAtomic(const Instruction *I) const override;
 
-  Instruction *
-  emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
-                   AtomicOrdering Ord) const override;
-  Instruction *
-  emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
-                    AtomicOrdering Ord) const override;
+  Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
+                                AtomicOrdering Ord) const override;
+  Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
+                                 AtomicOrdering Ord) const override;
 
   bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
                                   EVT VT) const override;