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Greg Roth
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[DirectX] Mark buffer load/store as mem read/write
By giving these intrinsics their appropriate attributes, loads of allocas that are stored on the other side of these calls can be eliminated. Adds a test that verifies that the unneeded loads can be eliminated and also that the attributes are set properly. Fixes #104271 This may be the first part of a broader audit of
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‎llvm/include/llvm/IR/IntrinsicsDirectX.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -28,12 +28,12 @@ def int_dx_handle_fromBinding
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[IntrNoMem]>;
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def int_dx_typedBufferLoad
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: DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_any_ty, llvm_i32_ty]>;
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: DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_any_ty, llvm_i32_ty], [IntrReadMem]>;
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def int_dx_typedBufferLoad_checkbit
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: DefaultAttrsIntrinsic<[llvm_any_ty, llvm_i1_ty],
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[llvm_any_ty, llvm_i32_ty]>;
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[llvm_any_ty, llvm_i32_ty], [IntrReadMem]>;
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def int_dx_typedBufferStore
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: DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_anyvector_ty]>;
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: DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_anyvector_ty], [IntrWriteMem]>;
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// Cast between target extension handle types and dxil-style opaque handles
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def int_dx_cast_handle : Intrinsic<[llvm_any_ty], [llvm_any_ty]>;

‎llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
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; RUN: opt -S -passes='early-cse<memssa>' %s | FileCheck %s
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; Ensure that EarlyCSE is able to eliminate unneeded loads of resource globals across typedBufferLoad.
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target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64"
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target triple = "dxilv1.6-unknown-shadermodel6.6-compute"
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%"class.hlsl::RWBuffer" = type { target("dx.TypedBuffer", <4 x float>, 1, 0, 0) }
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@In = global %"class.hlsl::RWBuffer" zeroinitializer, align 4
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@Out = global %"class.hlsl::RWBuffer" zeroinitializer, align 4
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; Function Attrs: convergent noinline norecurse
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; CHECK-LABEL define void @main()
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define void @main() local_unnamed_addr #0 {
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entry:
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%tmp = alloca target("dx.TypedBuffer", <4 x float>, 1, 0, 0), align 4
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%In_h.i = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false)
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store target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %In_h.i, ptr @In, align 4
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%Out_h.i = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0t(i32 4, i32 1, i32 1, i32 0, i1 false)
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store target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %Out_h.i, ptr @Out, align 4
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; CHECK: call i32 @llvm.dx.flattened.thread.id.in.group()
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%0 = call i32 @llvm.dx.flattened.thread.id.in.group()
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; CHECK-NOT: load {{.*}} ptr @In
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%1 = load target("dx.TypedBuffer", <4 x float>, 1, 0, 0), ptr @In, align 4
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; CHECK call noundef <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t
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%2 = call noundef <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %1, i32 %0)
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; CHECK-NOT: load {{.*}} ptr @In
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%3 = load target("dx.TypedBuffer", <4 x float>, 1, 0, 0), ptr @In, align 4
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%4 = call noundef <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %3, i32 %0)
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%add.i = fadd <4 x float> %2, %4
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store target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %Out_h.i, ptr %tmp, align 4
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call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %Out_h.i, i32 %0, <4 x float> %add.i)
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ret void
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}
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; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
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declare i32 @llvm.dx.flattened.thread.id.in.group() #1
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; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn
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; CHECK: declare <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32) [[ROAttr:#[0-9]+]]
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declare <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32) #2
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; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn
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; CHECK: declare void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32, <4 x float>) [[WOAttr:#[0-9]+]]
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declare void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32, <4 x float>) #2
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; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
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declare target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0t(i32, i32, i32, i32, i1) #3
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; CHECK: attributes [[ROAttr]] = { {{.*}} memory(read) }
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; CHECK: attributes [[WOAttr]] = { {{.*}} memory(write) }
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attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="8,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #1 = { mustprogress nofree nosync nounwind willreturn memory(none) }
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attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn }
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attributes #3 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
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!llvm.module.flags = !{!0, !1}
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!dx.valver = !{!2}
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!llvm.ident = !{!3}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 7, !"frame-pointer", i32 2}
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!2 = !{i32 1, i32 8}
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!3 = !{!"clang version 20.0.0git ([email protected]:llvm/llvm-project.git 54dc966bd3d375d7c1604fac5fdac20989c1072a)"}
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!4 = !{!5}
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!5 = distinct !{!5, !6, !"_ZN4hlsl8RWBufferIDv4_fEixEi: %agg.result"}
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!6 = distinct !{!6, !"_ZN4hlsl8RWBufferIDv4_fEixEi"}
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!7 = !{!8, !9, i64 0}
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!8 = !{!"_ZTSN4hlsl8RWBufferIDv4_fEE", !9, i64 0}
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!9 = !{!"omnipotent char", !10, i64 0}
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!10 = !{!"Simple C++ TBAA"}
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!11 = !{!12}
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!12 = distinct !{!12, !13, !"_ZN4hlsl8RWBufferIDv4_fEixEi: %agg.result"}
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!13 = distinct !{!13, !"_ZN4hlsl8RWBufferIDv4_fEixEi"}
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!14 = !{!15}
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!15 = distinct !{!15, !16, !"_ZN4hlsl8RWBufferIDv4_fEixEi: %agg.result"}
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!16 = distinct !{!16, !"_ZN4hlsl8RWBufferIDv4_fEixEi"}
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!17 = !{!18, !9, i64 0}
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!18 = !{!"_ZTSN4hlsl8__detail18TypedResourceProxyIU9_Res_u_CTDv4_fu17__hlsl_resource_tS2_EE", !9, i64 0, !19, i64 4}
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!19 = !{!"int", !9, i64 0}
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!20 = !{!21}
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!21 = distinct !{!21, !22, !"_ZN4hlsl8__detail18TypedResourceProxyIU9_Res_u_CTDv4_fu17__hlsl_resource_tS2_EaSES2_: %agg.result"}
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!22 = distinct !{!22, !"_ZN4hlsl8__detail18TypedResourceProxyIU9_Res_u_CTDv4_fu17__hlsl_resource_tS2_EaSES2_"}

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