Bugfix for FCLASS incorrect regbankselect; includes test file sed support similar to llc update script

lquinn2015 · lquinn2015 · commit 3799b2555ece · 2024-11-28T08:16:47.000-08:00
Signed-off-by: Luke Quinn &lt;quic_lquinn@quicinc.com&gt;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -151,6 +151,7 @@ bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
   switch (MI.getOpcode()) {
   case RISCV::G_FCVT_W_RV64:
   case RISCV::G_FCVT_WU_RV64:
+  case RISCV::G_FCLASS:
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_FCMP:
@@ -326,19 +327,21 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     // Use FPR64 for s64 loads on rv32.
     if (GPRSize == 32 && Size.getFixedValue() == 64) {
       assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
-      OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
+      OpdsMapping[0] = getFPValueMapping(Size);
       break;
     }
 
     // Check if that load feeds fp instructions.
     // In that case, we want the default mapping to be on FPR
     // instead of blind map every scalar to GPR.
-    if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI))
+    if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI)) {
       // If we have at least one direct use in a FP instruction,
       // assume this was a floating point load in the IR. If it was
       // not, we would have had a bitcast before reaching that
       // instruction.
-      OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
+      OpdsMapping[0] = getFPValueMapping(Size);
+      break;
+    }
 
     break;
   }
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
@@ -1,10 +1,10 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \
-# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
-# RUN:   -o - | FileCheck %s --check-prefixes=CHECK
-# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \
-# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
-# RUN:   -o - | FileCheck %s --check-prefixes=CHECK
+# RUN: sed 's/XLen/32/g' %s | llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs  -x mir \
+# RUN:   -o - | FileCheck %s --check-prefixes=CHECK-RV32
+# RUN: sed 's/XLen/64/g' %s | llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs -x mir \
+# RUN:   -o - | FileCheck %s --check-prefixes=CHECK-RV64
 
 ---
 name:            fp_store_fp_def_f32
@@ -14,15 +14,25 @@ body:             |
   bb.1:
     liveins: $x10, $f10_f, $f11_f
 
-    ; CHECK-LABEL: name: fp_store_fp_def_f32
-    ; CHECK: liveins: $x10, $f10_f, $f11_f
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
-    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY2]]
-    ; CHECK-NEXT: G_STORE [[FADD]](s32), [[COPY]](p0) :: (store (s32))
-    ; CHECK-NEXT: PseudoRET
+    ; CHECK-RV32-LABEL: name: fp_store_fp_def_f32
+    ; CHECK-RV32: liveins: $x10, $f10_f, $f11_f
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+    ; CHECK-RV32-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+    ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY2]]
+    ; CHECK-RV32-NEXT: G_STORE [[FADD]](s32), [[COPY]](p0) :: (store (s32))
+    ; CHECK-RV32-NEXT: PseudoRET
+    ;
+    ; CHECK-RV64-LABEL: name: fp_store_fp_def_f32
+    ; CHECK-RV64: liveins: $x10, $f10_f, $f11_f
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+    ; CHECK-RV64-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+    ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY2]]
+    ; CHECK-RV64-NEXT: G_STORE [[FADD]](s32), [[COPY]](p0) :: (store (s32))
+    ; CHECK-RV64-NEXT: PseudoRET
     %0:_(p0) = COPY $x10
     %1:_(s32) = COPY $f10_f
     %2:_(s32) = COPY $f11_f
@@ -39,15 +49,25 @@ body:             |
   bb.1:
     liveins: $x10, $f10_d, $f11_d
 
-    ; CHECK-LABEL: name: fp_store_fp_def_f64
-    ; CHECK: liveins: $x10, $f10_d, $f11_d
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
-    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY1]], [[COPY2]]
-    ; CHECK-NEXT: G_STORE [[FADD]](s64), [[COPY]](p0) :: (store (s64))
-    ; CHECK-NEXT: PseudoRET
+    ; CHECK-RV32-LABEL: name: fp_store_fp_def_f64
+    ; CHECK-RV32: liveins: $x10, $f10_d, $f11_d
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-RV32-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
+    ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY1]], [[COPY2]]
+    ; CHECK-RV32-NEXT: G_STORE [[FADD]](s64), [[COPY]](p0) :: (store (s64))
+    ; CHECK-RV32-NEXT: PseudoRET
+    ;
+    ; CHECK-RV64-LABEL: name: fp_store_fp_def_f64
+    ; CHECK-RV64: liveins: $x10, $f10_d, $f11_d
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-RV64-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
+    ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY1]], [[COPY2]]
+    ; CHECK-RV64-NEXT: G_STORE [[FADD]](s64), [[COPY]](p0) :: (store (s64))
+    ; CHECK-RV64-NEXT: PseudoRET
     %0:_(p0) = COPY $x10
     %1:_(s64) = COPY $f10_d
     %2:_(s64) = COPY $f11_d
@@ -64,13 +84,21 @@ body:             |
   bb.1:
     liveins: $x10, $f10_d
 
-    ; CHECK-LABEL: name: fp_store_no_def_f64
-    ; CHECK: liveins: $x10, $f10_d
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
-    ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
-    ; CHECK-NEXT: PseudoRET
+    ; CHECK-RV32-LABEL: name: fp_store_no_def_f64
+    ; CHECK-RV32: liveins: $x10, $f10_d
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-RV32-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
+    ; CHECK-RV32-NEXT: PseudoRET
+    ;
+    ; CHECK-RV64-LABEL: name: fp_store_no_def_f64
+    ; CHECK-RV64: liveins: $x10, $f10_d
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-RV64-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
+    ; CHECK-RV64-NEXT: PseudoRET
     %0:_(p0) = COPY $x10
     %1:_(s64) = COPY $f10_d
     G_STORE %1(s64), %0(p0) :: (store (s64))
@@ -85,15 +113,25 @@ body:             |
   bb.1:
     liveins: $x10, $f10_f
 
-    ; CHECK-LABEL: name: fp_load_fp_use_f32
-    ; CHECK: liveins: $x10, $f10_f
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
-    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
-    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[COPY1]]
-    ; CHECK-NEXT: $f10_f = COPY [[FADD]](s32)
-    ; CHECK-NEXT: PseudoRET implicit $f10_f
+    ; CHECK-RV32-LABEL: name: fp_load_fp_use_f32
+    ; CHECK-RV32: liveins: $x10, $f10_f
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+    ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+    ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[COPY1]]
+    ; CHECK-RV32-NEXT: $f10_f = COPY [[FADD]](s32)
+    ; CHECK-RV32-NEXT: PseudoRET implicit $f10_f
+    ;
+    ; CHECK-RV64-LABEL: name: fp_load_fp_use_f32
+    ; CHECK-RV64: liveins: $x10, $f10_f
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+    ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+    ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[COPY1]]
+    ; CHECK-RV64-NEXT: $f10_f = COPY [[FADD]](s32)
+    ; CHECK-RV64-NEXT: PseudoRET implicit $f10_f
     %0:_(p0) = COPY $x10
     %1:_(s32) = COPY $f10_f
     %2:_(s32) = G_LOAD %0(p0) :: (load (s32))
@@ -110,15 +148,25 @@ body:             |
   bb.1:
     liveins: $x10, $f10_d
 
-    ; CHECK-LABEL: name: fp_load_fp_use_f64
-    ; CHECK: liveins: $x10, $f10_d
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
-    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[LOAD]], [[COPY1]]
-    ; CHECK-NEXT: $f10_d = COPY [[FADD]](s64)
-    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    ; CHECK-RV32-LABEL: name: fp_load_fp_use_f64
+    ; CHECK-RV32: liveins: $x10, $f10_d
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+    ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[LOAD]], [[COPY1]]
+    ; CHECK-RV32-NEXT: $f10_d = COPY [[FADD]](s64)
+    ; CHECK-RV32-NEXT: PseudoRET implicit $f10_d
+    ;
+    ; CHECK-RV64-LABEL: name: fp_load_fp_use_f64
+    ; CHECK-RV64: liveins: $x10, $f10_d
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+    ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[LOAD]], [[COPY1]]
+    ; CHECK-RV64-NEXT: $f10_d = COPY [[FADD]](s64)
+    ; CHECK-RV64-NEXT: PseudoRET implicit $f10_d
     %0:_(p0) = COPY $x10
     %1:_(s64) = COPY $f10_d
     %2:_(s64) = G_LOAD %0(p0) :: (load (s64))
@@ -135,14 +183,23 @@ body:             |
   bb.1:
     liveins: $x10, $f10_d
 
-    ; CHECK-LABEL: name: fp_load_no_use_f64
-    ; CHECK: liveins: $x10, $f10_d
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
-    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
-    ; CHECK-NEXT: $f10_d = COPY [[LOAD]](s64)
-    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    ; CHECK-RV32-LABEL: name: fp_load_no_use_f64
+    ; CHECK-RV32: liveins: $x10, $f10_d
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+    ; CHECK-RV32-NEXT: $f10_d = COPY [[LOAD]](s64)
+    ; CHECK-RV32-NEXT: PseudoRET implicit $f10_d
+    ;
+    ; CHECK-RV64-LABEL: name: fp_load_no_use_f64
+    ; CHECK-RV64: liveins: $x10, $f10_d
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+    ; CHECK-RV64-NEXT: $f10_d = COPY [[LOAD]](s64)
+    ; CHECK-RV64-NEXT: PseudoRET implicit $f10_d
     %0:_(p0) = COPY $x10
     %1:_(s64) = COPY $f10_d
     %2:_(s64) = G_LOAD %0(p0) :: (load (s64))
@@ -158,15 +215,25 @@ body:             |
   bb.1:
     liveins: $x10, $f10_h, $f11_h
 
-    ; CHECK-LABEL: name: fp_store_fp_def_f16
-    ; CHECK: liveins: $x10, $f10_h, $f11_h
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f11_h
-    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY1]], [[COPY2]]
-    ; CHECK-NEXT: G_STORE [[FADD]](s16), [[COPY]](p0) :: (store (s16))
-    ; CHECK-NEXT: PseudoRET
+    ; CHECK-RV32-LABEL: name: fp_store_fp_def_f16
+    ; CHECK-RV32: liveins: $x10, $f10_h, $f11_h
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+    ; CHECK-RV32-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f11_h
+    ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY1]], [[COPY2]]
+    ; CHECK-RV32-NEXT: G_STORE [[FADD]](s16), [[COPY]](p0) :: (store (s16))
+    ; CHECK-RV32-NEXT: PseudoRET
+    ;
+    ; CHECK-RV64-LABEL: name: fp_store_fp_def_f16
+    ; CHECK-RV64: liveins: $x10, $f10_h, $f11_h
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+    ; CHECK-RV64-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f11_h
+    ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY1]], [[COPY2]]
+    ; CHECK-RV64-NEXT: G_STORE [[FADD]](s16), [[COPY]](p0) :: (store (s16))
+    ; CHECK-RV64-NEXT: PseudoRET
     %0:_(p0) = COPY $x10
     %1:_(s16) = COPY $f10_h
     %2:_(s16) = COPY $f11_h
@@ -183,15 +250,25 @@ body:             |
   bb.1:
     liveins: $x10, $f10_h
 
-    ; CHECK-LABEL: name: fp_load_fp_use_f16
-    ; CHECK: liveins: $x10, $f10_h
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
-    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
-    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[LOAD]], [[COPY1]]
-    ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16)
-    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    ; CHECK-RV32-LABEL: name: fp_load_fp_use_f16
+    ; CHECK-RV32: liveins: $x10, $f10_h
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+    ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+    ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[LOAD]], [[COPY1]]
+    ; CHECK-RV32-NEXT: $f10_h = COPY [[FADD]](s16)
+    ; CHECK-RV32-NEXT: PseudoRET implicit $f10_h
+    ;
+    ; CHECK-RV64-LABEL: name: fp_load_fp_use_f16
+    ; CHECK-RV64: liveins: $x10, $f10_h
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+    ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+    ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[LOAD]], [[COPY1]]
+    ; CHECK-RV64-NEXT: $f10_h = COPY [[FADD]](s16)
+    ; CHECK-RV64-NEXT: PseudoRET implicit $f10_h
     %0:_(p0) = COPY $x10
     %1:_(s16) = COPY $f10_h
     %2:_(s16) = G_LOAD %0(p0) :: (load (s16))
@@ -200,3 +277,49 @@ body:             |
     PseudoRET implicit $f10_h
 
 ...
+---
+name:            fpclass
+legalized:       true
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x10' }
+body:             |
+  bb.1:
+    liveins: $x10
+
+    ; CHECK-RV32-LABEL: name: fpclass
+    ; CHECK-RV32: liveins: $x10
+    ; CHECK-RV32-NEXT: {{  $}}
+    ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+    ; CHECK-RV32-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 927
+    ; CHECK-RV32-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+    ; CHECK-RV32-NEXT: [[FCLASS:%[0-9]+]]:gprb(s32) = G_FCLASS [[LOAD]](s32)
+    ; CHECK-RV32-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[FCLASS]], [[C]]
+    ; CHECK-RV32-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
+    ; CHECK-RV32-NEXT: $x10 = COPY [[ICMP]](s32)
+    ; CHECK-RV32-NEXT: PseudoRET implicit $x10
+    ;
+    ; CHECK-RV64-LABEL: name: fpclass
+    ; CHECK-RV64: liveins: $x10
+    ; CHECK-RV64-NEXT: {{  $}}
+    ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+    ; CHECK-RV64-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 927
+    ; CHECK-RV64-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0
+    ; CHECK-RV64-NEXT: [[FCLASS:%[0-9]+]]:gprb(s64) = G_FCLASS [[LOAD]](s32)
+    ; CHECK-RV64-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[FCLASS]], [[C]]
+    ; CHECK-RV64-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]]
+    ; CHECK-RV64-NEXT: $x10 = COPY [[ICMP]](s64)
+    ; CHECK-RV64-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s32) = G_LOAD %0(p0) :: (load (s32))
+    %4:_(sXLen) = G_CONSTANT iXLen 927
+    %5:_(sXLen) = G_CONSTANT iXLen 0
+    %6:_(sXLen) = G_FCLASS %1(s32)
+    %7:_(sXLen) = G_AND %6, %4
+    %8:_(sXLen) = G_ICMP intpred(ne), %7(sXLen), %5
+    $x10 = COPY %8(sXLen)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/utils/update_mir_test_checks.py b/llvm/utils/update_mir_test_checks.py
